How can I get a ddr sdram controller for the MT46V16M16TG -75 micron chip. I want a controller without the plb or opb interface. I tried open cores.org but it says that the repository is empty with no files pertaining to the ddrsdram controller core. Could someone give me right pointers? Thanks, D.
ddr sdram controller
Started by ●March 10, 2007
Reply by ●March 10, 20072007-03-10
<dhruvakshad@gmail.com> wrote in message news:1173559475.001130.307290@v33g2000cwv.googlegroups.com...> How can I get a ddr sdram controller for the MT46V16M16TG -75 micron > chip. > I want a controller without the plb or opb interface. I tried open > cores.org but it says that the repository is empty with no files > pertaining to the ddrsdram controller core. > Could someone give me right pointers? > Thanks, > D. >Easiest way is to download data sheet from Micron site and put it together yourself. I recently put together a controller for the Micron MT48H4M16LF mobile SDRAM which will be similar. Took about a day to put together via schematics and simulated. I imagine a Verilog/VHDL whizz could do it a lot quicker.
Reply by ●March 10, 20072007-03-10
dhruvakshad@gmail.com wrote:> How can I get a ddr sdram controller for the MT46V16M16TG -75 micron > chip. > I want a controller without the plb or opb interface. I tried open > cores.org but it says that the repository is empty with no files > pertaining to the ddrsdram controller core. > Could someone give me right pointers? > Thanks, > D.I read a few reports about that controller, it seemed to be a rather low-performance option. You could look into Xilinx's MIG, that could help to get you started - I started building my own 200MHz DDR controller to interface with a 256MB PC3200 DIMM and I use an MIG design as a reference when I need inspiration. Again, I am not using the MIG either since I have seen mixed feedback about it. I too would be interested in hearing about existing open-source, preferably high-bandwidth, DDR controllers. Right now, I am expecting the my controller to consume about 44 of 144 BRAMs (ouch!) and at least 3000 of 13.6k slices on my XC2VP30-7. Things would be much simpler if I had V5s instead. I am doing this mostly because I have always been pretty far from IOBs in my previous FPGA/ASIC jobs. Since knowledge of DDR/DDR2 is often a must for the jobs I am interested in, I decided to try building a full-blown DDR controller - I'll most likely downscale it for actual use though. Since your device is only 16bits wide, things should be much simpler and you should have many more options than I do. If you browse OpenCore's CVS directory, you will find many SDR-SDRAM controllers that may be nearly suitable for your application - you should be able to modify one of the many SDR controllers for DDR operation by doing little more than changing the IOB FFs and widening data buses as necessary. Note: they appear to all be verilog. BTW, all DDR-SDRAM devices are pretty much the same, there should be no need to request one for a specific device. All you need to do is connect a generic DDR controller to a suitable clock and modify the controller to match the CAS/RAS and other latency requirements of your specific device for the selected operating frequency.
Reply by ●March 11, 20072007-03-11
Daniel S. wrote:> dhruvakshad@gmail.com wrote: >> How can I get a ddr sdram controller for the MT46V16M16TG -75 micron >> chip. >> I want a controller without the plb or opb interface. I tried open >> cores.org but it says that the repository is empty with no files >> pertaining to the ddrsdram controller core. >> Could someone give me right pointers? >> Thanks, >> D. > > I read a few reports about that controller, it seemed to be a rather > low-performance option. You could look into Xilinx's MIG, that could > help to get you started - I started building my own 200MHz DDR > controller to interface with a 256MB PC3200 DIMM and I use an MIG design > as a reference when I need inspiration. Again, I am not using the MIG > either since I have seen mixed feedback about it. I too would be > interested in hearing about existing open-source, preferably > high-bandwidth, DDR controllers. > > Right now, I am expecting the my controller to consume about 44 of 144 > BRAMs (ouch!) and at least 3000 of 13.6k slices on my XC2VP30-7. Things > would be much simpler if I had V5s instead. I am doing this mostly > because I have always been pretty far from IOBs in my previous FPGA/ASIC > jobs. Since knowledge of DDR/DDR2 is often a must for the jobs I am > interested in, I decided to try building a full-blown DDR controller - > I'll most likely downscale it for actual use though. > > Since your device is only 16bits wide, things should be much simpler and > you should have many more options than I do. If you browse OpenCore's > CVS directory, you will find many SDR-SDRAM controllers that may be > nearly suitable for your application - you should be able to modify one > of the many SDR controllers for DDR operation by doing little more than > changing the IOB FFs and widening data buses as necessary. Note: they > appear to all be verilog. > > BTW, all DDR-SDRAM devices are pretty much the same, there should be no > need to request one for a specific device. All you need to do is connect > a generic DDR controller to a suitable clock and modify the controller > to match the CAS/RAS and other latency requirements of your specific > device for the selected operating frequency.DDR controllers should simply meet the requirements of the JEDEC spec (you can find it at Micron). As you want to get faster things get more complex of course. There are two primary differences between SDR and DDR: 1. The clock is complementary and should have very low skew between the pair. In addition, clocking at the SDRAM is based on the differential voltage between the clock pair rather than VIL/VIH. 2. The strobes (DQS rather than DQM) are driven by the SDRAM during reads (with interesting timing that has to be accounted for at the controller).i.e. the strobes are bidirectional. The interesting timing is that the strobes are driven coincidentally with the data during reads, and that has to be offset at the controller to capture the data successfully. Most controllers assert the strobe during writes at roughly 50% of the data window. Delay units in the FPGA are a godsend for this sort of thing. Starting with a SDR controller, the spec and a typical device data sheet it shouldn't be too hard a task to do a DDR controller. How well it performs depends on the device and implementation, of course. Cheers PeteS
Reply by ●March 13, 20072007-03-13
On Mar 11, 1:44 am, dhruvaks...@gmail.com wrote:> How can I get a ddr sdram controller for the MT46V16M16TG -75 micron > chip. > I want a controller without the plb or opb interface. I tried open > cores.org but it says that the repository is empty with no files > pertaining to the ddrsdram controller core. > Could someone give me right pointers? > Thanks, > D.You might want to have a look at Xilinx website itself. Its not very high performance, but gives a good heads up.
Reply by ●March 16, 20072007-03-16
Hi all, Thanks a lot guys for the response. I am currently changing the plb_ddr controller by removing the plb side interface and integrating the ddr interface into my code. D On Mar 13, 3:05 am, birla.man...@gmail.com wrote:> On Mar 11, 1:44 am,dhruvaks...@gmail.com wrote: > > > How can I get a ddr sdram controller for the MT46V16M16TG -75 micron > > chip. > > I want a controller without the plb or opb interface. I tried open > > cores.org but it says that the repository is empty with no files > > pertaining to the ddrsdram controller core. > > Could someone give me right pointers? > > Thanks, > > D. > > You might want to have a look at Xilinx website itself. Its not very > high performance, but gives a good heads up.
