CPLD + =?UTF-8?B?wrVDIHdpdGggcmVhc29uYWJseS1wcmljZWQgdG9vbHM/?=

-jg wrote:
> 
> You need to define just how much the CPLD portion needs to DO.
> - ie how many macrocells are needed
> How much memory is shared, and what bandwdith is needed ?
> 
> It is quite easy to set up shared memory access on a Microcontroller,
> with external RAM and a CPLD -  choose a fast SRAM, and lock the
> CPLD access to the idle periods in the uC bus - that way,
> you emulate dual-port memory with cheap SRAM.
> 

Yes, I've pretty much independently come to the same conclusion.  This 
is most likely the sanest option.

The next step is to prototype the CPLD code and see what kind of CPLD it 
can fit into.

The only potential concern with having the CPLD do the arbitration of 
the SRAM bus is needing too many I/O pins on the CPLD, but I'm sure that 
can be dealt with, too.

	-hpa

H. Peter Anvin <hpa@zytor.com> wrote:
...
> The only potential concern with having the CPLD do the arbitration of 
> the SRAM bus is needing too many I/O pins on the CPLD, but I'm sure that 
> can be dealt with, too.

Go with an FPGA. Some more external infrastructure needed, but much
more possibilities...
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

On 4=A4=EB13=A4=E9, =A4W=A4=C82=AE=C917=A4=C0, "H. Peter Anvin" <h...@zytor=
.com> wrote:
> -jg wrote:
>
> > You need to define just how much theCPLDportion needs to DO.
> > - ie how many macrocells are needed
> > How much memory is shared, and what bandwdith is needed ?
>
> > It is quite easy to set up shared memory access on a Microcontroller,
> > with external RAM and aCPLD-  choose a fast SRAM, and lock the
> >CPLDaccess to the idle periods in the uC bus - that way,
> > you emulate dual-port memory with cheap SRAM.
>
> Yes, I've pretty much independently come to the same conclusion.  This
> is most likely the sanest option.
>
> The next step is to prototype theCPLDcode and see what kind ofCPLDit
> can fit into.
>
> The only potential concern with having theCPLDdo the arbitration of
> the SRAM bus is needing too many I/O pins on theCPLD, but I'm sure that
> can be dealt with, too.
>
>         -hpa

    regards:

          good answer