DDR2 with Spartan-3A anybody having success??

I understand that mig generated testbench is rather frustrating ;
but that being said, my question remains : is that code (35 files,
well documented, in verilog or vhdl) a good starting point for an
implementation of a ddr2 controller, or not ? Is there a DDR2 better
controller pattern somewhere ?

and another question, why memory manufacturers (micron) didn't provide
hdl wrappers for their components ?