Xilinx EDK: Slow OPB write speeds

Well, I got nearly the same results for interrupt dispatching both
over OPB & DCR. Eventually I hooked up my high-speed ADC & DAC drivers
to PLB though I'm kinda already overloading my PLB (got some off-chip
SRAM). It seems that every design should be centered around minimizing
memory transactions which implies using buffers intensively and later
communicate results in a bursty manner. Still I think---in some
circumstances---this kinda defeats the purpose of having a powerful 32-
bit uP core at your disposal and reduces it to mere supervisory tasks!