Aldec ActiveHDL vs. ModelSim

I currently use Altera Quartus along with ModelSim for FPGA designs
using Verilog.  In ModelSim I use the "$random" term to create a
random driver.  My company is considering updating its tools so that
we can get code coverage capabilities and possibly automatically
generate block diagrams from the Verilog code.  I've looked into Aldec
ActiveHDL and it seems like most of this software provided redundant
functionality to that of Altera Quartus.  So strictly from a
simulation and code coverage standpoint which tool is better,
considering that I would like to use Verilog/SystemVerilog for a
random driven, self-checking simulation environment?  Does Aldec
support random stimuli in their tool outside of using SystemC?

spgoldman@gmail.com wrote:

> I currently use Altera Quartus along with ModelSim for FPGA designs
> using Verilog.  In ModelSim I use the "$random" term to create a
> random driver.  My company is considering updating its tools so that
> we can get code coverage capabilities and possibly automatically
> generate block diagrams from the Verilog code.  I've looked into Aldec
> ActiveHDL and it seems like most of this software provided redundant
> functionality to that of Altera Quartus.  So strictly from a
> simulation and code coverage standpoint which tool is better,
> considering that I would like to use Verilog/SystemVerilog for a
> random driven, self-checking simulation environment?  Does Aldec
> support random stimuli in their tool outside of using SystemC?
> 

I use Aldec for nearly all of my simulation (I have a Modelsim PE seat 
as well).  For VHDL, I use the uniform function in Math_real to generate 
my randoms in testbenches, as that is well supported across different 
tools, including both Modelsim and Aldec.