G'day (o; Just got the confirmation that ispLever 7.0 is broken for mixed Verilog/VHDL designs...my case was that a VHDL T80 Z80 CPU core module wrapped in a Verilog top file would fail with Precision unable to find work library... Now with the patch it's running through (o; Either contact Lattice for a fix if you have this issue or wait until end of year for ispLever 7.1 (o; cheers rick
mixed Verilog/VHDL in ispLever 7.0 broken
Started by ●August 14, 2007
Reply by ●August 14, 20072007-08-14
On 14 Aug, 09:35, Richard Klingler <m...@aol.com> wrote:> G'day (o; > > Just got the confirmation that ispLever 7.0 is broken for > mixed Verilog/VHDL designs...my case was that a VHDL T80 > Z80 CPU core module wrapped in a Verilog top file would > fail with Precision unable to find work library... > > Now with the patch it's running through (o; > > Either contact Lattice for a fix if you have this issue > or wait until end of year for ispLever 7.1 (o;Is it ispLever or Precision that is the problem. Does Synplify work better? Jon
Reply by ●August 14, 20072007-08-14
Jon Beniston wrote:> On 14 Aug, 09:35, Richard Klingler <m...@aol.com> wrote: >> G'day (o; >> >> Just got the confirmation that ispLever 7.0 is broken for >> mixed Verilog/VHDL designs...my case was that a VHDL T80 >> Z80 CPU core module wrapped in a Verilog top file would >> fail with Precision unable to find work library... >> >> Now with the patch it's running through (o; >> >> Either contact Lattice for a fix if you have this issue >> or wait until end of year for ispLever 7.1 (o; > > Is it ispLever or Precision that is the problem. Does Synplify work > better? > > Jon >From the patched files it looks like an ispLever problem as no Precision files are included... Dunno if Synplify works better as you have to install the full version for this feature... cheers rick
