Low-level FPGA programming?

Hi.
It is possible to have a format of .pof/.sof files from Altera, thus,
to decompile some ready projects and try to make our own, omitting
Altera software tools?

> It is possible to have a format of .pof/.sof files from Altera, thus,
> to decompile some ready projects and try to make our own, omitting
> Altera software tools?

No, we do not give out the format of the POF/SOF.

Sorry,

Paul Leventis
Altera Corp.

> It is possible to have a format of .pof/.sof files from Altera, thus,
> to decompile some ready projects and try to make our own, omitting
> Altera software tools?

BTW, is the same possible with Xilinx?

On 2007-09-03, drop669@gmail.com <drop669@gmail.com> wrote:
>> It is possible to have a format of .pof/.sof files from Altera, thus,
>> to decompile some ready projects and try to make our own, omitting
>> Altera software tools?
>
> BTW, is the same possible with Xilinx?

I don't know what kind of format .pof/.sof is, but for Xilinx you have
the xdl tool available that can convert a .ncd file into a .xdl file.

The .xdl file will contain an ASCII representation of your place and
routed circuit. (You can also do it before routing to only get the
mapped circuit.)

You might also be interested in JBits (Java library for manipulating
Xilinx design. Sadly it has been discontinued and does not support
anything newer than Virtex-II.) ABits might also be interesting
if you are interested in Atmel FPGAs. (Google ABits and Atmel.)

I have also seen that some people have reverse engineered part of the
Xilinx bitstream format. There was a link to a "debit" utility posted
a couple of month ago which could take a .bit file and present a view
similar to the FPGA editor. The website was quickly taken down and the
author said that he didn't intend the tool to become publicly known
before it was more finished if I remember correctly. Debit was
available at http://www.ulogic.org/trac before it disappeared.

I also saw that at least one research group at FPL 2007 had done some
reverse engineering of the Xilinx Bitstream format. Not sure if they
are affiliated with "debit" or not.


(If you are interested in the XDL format I have written a small library
in Python that can do some simple manipulation of XDL files. It is
enough to insert a logic analyzer into a placed and routed design.
It is not quite cleaned up yet but it should be released before
FPGAworld in Stockholm this year. (before 13th september))

/Andreas

<drop669@gmail.com> wrote in message 
news:1188777964.492149.314030@g4g2000hsf.googlegroups.com...
> Hi.
> It is possible to have a format of .pof/.sof files from Altera, thus,
> to decompile some ready projects and try to make our own, omitting
> Altera software tools?
>

It would be theoretically possible, but definitley a non-trivial exercise.

You've probably noticed the variation in pof/sof size depending on the
target chip?
You could start by trying various combinations of logic, with forced
placement in the same area on the FPGA and see how it changes the
format of the pof/sof file.
Similarly, repeat the same logic combinations in different areas, and look
for repeating pattern in the pof/sof files.

-----

Why bother when the tools are (basically) free from ALTERA , and of
a very high quality anyway? (imho)

Red

Andreas,

Per the license agreement that one signs to get the software, 'reverse 
engineering' is a violation.

Xilinx zealously protects its intellectual property through the means 
available to us.

http://www.xilinx.com/ise/license/license_agreement.htm

"3. Restrictions. To protect the Intellectual Property contained in the 
Software, you may not decompile, translate, reverse-engineer, 
disassemble, or otherwise reduce the Software, data files generated by 
the Software, and/or programmable hardware devices, transmit the 
Software or display the object code of the Software on any computer 
screen, or to make any hard-copy memory dumps of the object code. You 
may not, in whole or in part, modify or prepare derivative works of the 
Software. You may not publish or disclose the results of any 
benchmarking of the Software, or use such results for any other software 
development activities. You may not make any copies of the Software, 
except to the extent necessary to be used on separate non-simultaneous 
computers as permitted herein, and one (1) copy of the Software in 
machine-readable form solely for backup purposes."

Austin

> "3. Restrictions. To protect the Intellectual Property contained in the
> Software, you may not decompile, translate, reverse-engineer,
> disassemble, or otherwise reduce the Software, data files generated by
> the Software,

So you're not allowed to translate data files produced by the
software. Sounds like no one can legally produce an bitstream then.
Can I get a refund?

Jon

On 2007-09-03, austin <austin@xilinx.com> wrote:
> "3. Restrictions. To protect the Intellectual Property contained in the 
> Software, you may not decompile, translate, reverse-engineer, 
> disassemble, or otherwise reduce the Software, data files generated by 
> the Software, and/or programmable hardware devices, transmit the 

Just a quick follow up to this posting, I didn't want to say anything more
until I knew more about.

I have finally been able to confirm with Xilinx that "data files generated
by the Software" is not intended to include XDL files.

Austin: Thanks for helping me get in touch with the right people.

/Andreas

On Sep 3, 11:17 am, austin <aus...@xilinx.com> wrote:
> Andreas,
>
> Per the license agreement that one signs to get the software, 'reverse
> engineering' is a violation.

License agreements contain all sort of over-reaching unenforceable
nonsense...

Of course figuring out what is and isn't isn't trivially, but a good
portions of it is nothing but FUD.

Keep in mind that there are some explicit exemptions in law for
reverse engineering for purposes of interoperability, but again
figuring out how those match up against over reaching vendor claims is
non trivial.

Andreas Ehliar <ehliar@lysator.liu.se> writes:
> I have also seen that some people have reverse engineered part of the
> Xilinx bitstream format. There was a link to a "debit" utility posted
> a couple of month ago which could take a .bit file and present a view
> similar to the FPGA editor. The website was quickly taken down and the
> author said that he didn't intend the tool to become publicly known
> before it was more finished if I remember correctly. Debit was
> available at http://www.ulogic.org/trac before it disappeared.

It appears to be back now.

  - a

-- 
PGP/GPG: 5C9F F366 C9CF 2145 E770  B1B8 EFB1 462D A146 C380