Problem locking a DCM driven by FX output of another DCM

I have a design with 3 DCMs. The first DCM generates 280 MHz out of 210 MHz. 
It is then divided by 2 and 4 in a PMCD. There are 2 more DCMs, one driven 
by resulting 70 MHz clock and another by 140 MHz clock. Both have problem 
locking. Their resets are slightly delayed and negated locked condition of 
the first DCM. As it stands now I need to reset the first DCM a few times 
until I get all 3 locked (the first DCM locks every time easily). The 
frequency ranges for all of the DCMs seem to be set correctly.

Any ideas?


Thanks,
/Mikhail 

Forgot to mention that it is all taking place in a V4 device...

/Mikhail 

On Sep 6, 1:56 pm, "MM" <mb...@yahoo.com> wrote:
> Forgot to mention that it is all taking place in a V4 device...
>
> /Mikhail



The FX output jitter spec of the DCMs does not meet the input jitter
requirements of the DCMs.  What you are trying to do will not work
reliably.

Regards,

John McCaskill
www.fastertechnology.com

"John McCaskill" <jhmccaskill@gmail.com> wrote in message 
news:1189105528.073561.184050@d55g2000hsg.googlegroups.com...
>
> The FX output jitter spec of the DCMs does not meet the input jitter
> requirements of the DCMs.  What you are trying to do will not work
> reliably.

Yes, I remember reading it... So, no hope here? Anyone from Xilinx? I don't 
care much about the output jitter on the two DCMs, I just need them to 
produce the clocks at right frequencies.... If I can't do it, I am in real 
trouble...


Thanks,
/Mikhail

On Sep 6, 2:11 pm, "MM" <mb...@yahoo.com> wrote:
> "John McCaskill" <jhmccask...@gmail.com> wrote in message
>
> news:1189105528.073561.184050@d55g2000hsg.googlegroups.com...
>
>
>
> > The FX output jitter spec of the DCMs does not meet the input jitter
> > requirements of the DCMs.  What you are trying to do will not work
> > reliably.
>
> Yes, I remember reading it... So, no hope here? Anyone from Xilinx? I don't
> care much about the output jitter on the two DCMs, I just need them to
> produce the clocks at right frequencies.... If I can't do it, I am in real
> trouble...
>
> Thanks,
> /Mikhail



Skip the first DCM, and use the other two in FX mode.  If they do not
lock in the phase relationship that you need, reset one of them.

Regards,

John McCaskill
www.fastertechnology.com

"John McCaskill" <jhmccaskill@gmail.com> wrote in message 
news:1189106556.202143.39700@o80g2000hse.googlegroups.com...
>
> Skip the first DCM, and use the other two in FX mode.  If they do not
> lock in the phase relationship that you need, reset one of them.

The problem is not so much in the phase, but in the CLKFX_DIVIDE and 
CLKFX_MULTIPLY values I need to get the required frequencies. The maximim 
CLKFX_DIVIDE is not big enough to allow for what you are suggesting... I've 
actually spent a lot of time trying to avoid the first DCM, but couldn't 
find a solution.


/Mikhail

"MM" <mbmsv@yahoo.com> wrote in message 
news:5kb1oeF2ut3mU1@mid.individual.net...
> "John McCaskill" <jhmccaskill@gmail.com> wrote in message 
> news:1189105528.073561.184050@d55g2000hsg.googlegroups.com...
>>
>> The FX output jitter spec of the DCMs does not meet the input jitter
>> requirements of the DCMs.  What you are trying to do will not work
>> reliably.
>
> Yes, I remember reading it... So, no hope here? Anyone from Xilinx? I 
> don't care much about the output jitter on the two DCMs, I just need them 
> to produce the clocks at right frequencies.... If I can't do it, I am in 
> real trouble...
>
>
> Thanks,
> /Mikhail

I agree with John McCaskill.  If you can't generate your later clocks in FX 
mode from the initial clock, you can't get there from here.

What is the system input and DCM output frequencies you need?  Must they be 
phase aligned?

If the design can still be altered, a different clock might be used to feed 
the DCMs in the first place (such as 70 MHz to generate all the clocks, even 
what was the system clock) or go through an external jitter clean-up clock 
chip to then feed the DCMs.

With the architecture fixed as it is now, it won't work.

- John_H 

On Sep 6, 2:40 pm, "MM" <mb...@yahoo.com> wrote:
> "John McCaskill" <jhmccask...@gmail.com> wrote in message
>
> news:1189106556.202143.39700@o80g2000hse.googlegroups.com...
>
>
>
> > Skip the first DCM, and use the other two in FX mode.  If they do not
> > lock in the phase relationship that you need, reset one of them.
>
> The problem is not so much in the phase, but in the CLKFX_DIVIDE and
> CLKFX_MULTIPLY values I need to get the required frequencies. The maximim
> CLKFX_DIVIDE is not big enough to allow for what you are suggesting... I've
> actually spent a lot of time trying to avoid the first DCM, but couldn't
> find a solution.
>
> /Mikhail

2/3 and 2/6 should get you there.  I think that those are valid
combinations for M and D.

2/3 * 210 = 140
2/6 * 210 = 70


Regards,

John McCaskill
www.fastertechnology.com

"John McCaskill" <jhmccaskill@gmail.com> wrote in message 
news:1189108426.459585.116970@w3g2000hsg.googlegroups.com...
>
> 2/3 and 2/6 should get you there.  I think that those are valid
> combinations for M and D.
>
> 2/3 * 210 = 140
> 2/6 * 210 = 70
>

Not sure what you are trying to say here... This is pretty much what my 
first DCM with PMCD is doing. The final clocks are (70/29)*16 and 
(140/29)*20.

/Mikhail 

"John_H" <newsgroup@johnhandwork.com> wrote in message 
news:13e0m5eprs3aje6@corp.supernews.com...
>
> If the design can still be altered, a different clock might be used to 
> feed the DCMs in the first place (such as 70 MHz to generate all the 
> clocks, even what was the system clock) or go through an external jitter 
> clean-up clock chip to then feed the DCMs.
>
> With the architecture fixed as it is now, it won't work.

The design can be altered but at a high cost, as I will need to redesign 
many other pieces...

/Mikhail