Hi, I'm working on design with LVDS signals and when I'm trying to place LVDS inputs at dedicated pins I got : Error: Non-differential I/O pin addr[8] in pin location 86 and pad 103 too close to differential I/O pin clk_pll(n) in pin location 90 and pad 107 -- pins must be separated by a minimum of 4 pads And I don't know why ? How can it be too close ? Is any workaround for this ? (CYCLON II 2C5) Adam
LVDS pin placing on CYCLON II problem
Started by ●September 10, 2007
Reply by ●September 10, 20072007-09-10
Quartus will not allow a non-differential signals within I believe 4 pins of a differential signal. The solution is to move the single-ended signal away from the differential pair. The reason for this has to do with maintaining the integrity of the differential signal. A single ended signal running next to either the positive or negative end of a diff pair could induce single ended noise; and diff signals are only good at rejecting common-mode noise. Something else to beware of, depending on the device and whether the differential signals are inputs or outputs, is that the bank voltage where the differential signals reside may have to be powered by 2.5V. This may negatively impact your single ended signal causing it not to meet the VINhi levels of the device it is tied to. "G�rski Adam" <gorskia@.................wp....................pl..................> wrote in message news:fc3jmt$4s8$1@atlantis.news.tpi.pl...> Hi, > > I'm working on design with LVDS signals and when I'm trying to place LVDS > inputs at dedicated pins I got : > > Error: Non-differential I/O pin addr[8] in pin location 86 and pad 103 too > close to differential I/O pin clk_pll(n) in pin location 90 and pad 107 -- > pins must be separated by a minimum of 4 pads > > > And I don't know why ? How can it be too close ? Is any workaround for > this ? (CYCLON II 2C5) > > Adam
Reply by ●September 11, 20072007-09-11
Hi, Yes, that's true. But what I can't place very low speed signals (like reset) next to LVDS? I don't know. But anyway I found solution for this and I can force fitter to place such signals next to LVDS pair. For such signal TOGGLE RATE must be defined to 0 MHz. Thx , Adam> Quartus will not allow a non-differential signals within I believe 4 pins of > a differential signal. The solution is to move the single-ended signal away > from the differential pair. The reason for this has to do with maintaining > the integrity of the differential signal. A single ended signal running > next to either the positive or negative end of a diff pair could induce > single ended noise; and diff signals are only good at rejecting common-mode > noise. > > Something else to beware of, depending on the device and whether the > differential signals are inputs or outputs, is that the bank voltage where > the differential signals reside may have to be powered by 2.5V. This may > negatively impact your single ended signal causing it not to meet the VINhi > levels of the device it is tied to. > > > > > "G�rski Adam" > <gorskia@.................wp....................pl..................> wrote > in message news:fc3jmt$4s8$1@atlantis.news.tpi.pl... >> Hi, >> >> I'm working on design with LVDS signals and when I'm trying to place LVDS >> inputs at dedicated pins I got : >> >> Error: Non-differential I/O pin addr[8] in pin location 86 and pad 103 too >> close to differential I/O pin clk_pll(n) in pin location 90 and pad 107 -- >> pins must be separated by a minimum of 4 pads >> >> >> And I don't know why ? How can it be too close ? Is any workaround for >> this ? (CYCLON II 2C5) >> >> Adam > >
Reply by ●September 11, 20072007-09-11
G�rski Adam pisze:> Hi, > > Yes, that's true. > But what I can't place very low speed signals (like reset) next to LVDS?> But *why* I can't place very low speed signals (like reset) next to LVDS? > I don't know.> I don't know. > > But anyway I found solution for this and I can force fitter to place > such signals next to LVDS pair. > > For such signal TOGGLE RATE must be defined to 0 MHz. > > Thx , > > Adam > >> Quartus will not allow a non-differential signals within I believe 4 >> pins of a differential signal. The solution is to move the >> single-ended signal away from the differential pair. The reason for >> this has to do with maintaining the integrity of the differential >> signal. A single ended signal running next to either the positive or >> negative end of a diff pair could induce single ended noise; and diff >> signals are only good at rejecting common-mode noise. >> >> Something else to beware of, depending on the device and whether the >> differential signals are inputs or outputs, is that the bank voltage >> where the differential signals reside may have to be powered by 2.5V. >> This may negatively impact your single ended signal causing it not to >> meet the VINhi levels of the device it is tied to. >> >> >> >> >> "G�rski Adam" >> <gorskia@.................wp....................pl..................> >> wrote in message news:fc3jmt$4s8$1@atlantis.news.tpi.pl... >>> Hi, >>> >>> I'm working on design with LVDS signals and when I'm trying to place >>> LVDS inputs at dedicated pins I got : >>> >>> Error: Non-differential I/O pin addr[8] in pin location 86 and pad >>> 103 too close to differential I/O pin clk_pll(n) in pin location 90 >>> and pad 107 -- pins must be separated by a minimum of 4 pads >>> >>> >>> And I don't know why ? How can it be too close ? Is any workaround >>> for this ? (CYCLON II 2C5) >>> >>> Adam >> >>
