Hello I am trying to convert the following code to vhdl assign Q = (rst==0)?Q_int:1'do; How do i convert this to vhdl? I have to use a concurrent statement as this statement is not in the always block hence concurrent. I cannot use an if then else statement as it is sequential. Please help
converting verilog to vhdl
Started by ●December 4, 2007
Reply by ●December 4, 20072007-12-04
Anuja wrote:> assign Q = (rst==0)?Q_int:1'do; > > How do i convert this to vhdl? I have to use a concurrent statement asQ <= Q_int when rst = '0' else '0';
Reply by ●December 6, 20072007-12-06
For future reference this is called conditional assignment. Next time you can just google "VHDL conditional assignment". ---Matthew Hicks> Hello > > I am trying to convert the following code to vhdl > > assign Q = (rst==0)?Q_int:1'do; > > How do i convert this to vhdl? I have to use a concurrent statement as > this statement is not in the always block hence concurrent. I cannot > use an if then else statement as it is sequential. > > Please help >
Reply by ●December 6, 20072007-12-06
On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote:> Anuja wrote: > > assign Q = (rst==0)?Q_int:1'do; > > > How do i convert this to vhdl? I have to use a concurrent statement as > > Q <= Q_int when rst = '0' else '0';Hi, I am having simulation problems with my code. I am trying to convert Verilog code to VHDL. I can compile correctly. When i simulate the following code in VHDL, value of Q_int is stuck at "00". It does not change at all. Please let me know what the problem could be. Thanks for all your help Verilog code => module Reg2(Q, D, en, rst, clk); parameter REGWIDTH = 2; input clk, en, rst; input [(REGWIDTH-1):0] D; output [(REGWIDTH-1):0] Q; reg [(REGWIDTH-1):0] Q_int; assign Q = (rst == 0)? Q_int : 2'd0; always @ (posedge clk) begin if (rst == 1) Q_int <= 2'd0; else if (en == 1) Q_int <= D; else Q_int <= Q_int; end endmodule VHDL code => LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Reg2 IS PORT( clk, rst, en : IN std_logic; D : IN std_logic_vector(1 downto 0); Q : OUT std_logic_vector(1 downto 0) ); END Reg2; ARCHITECTURE behavioral OF Reg2 IS -- register and constant declaration SIGNAL Q_int : std_logic_vector(1 downto 0); CONSTANT LO : std_logic := '0'; CONSTANT HI : std_logic := '1'; BEGIN Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00"; one : PROCESS (clk) BEGIN IF (clk = HI and clk'event) THEN IF (rst = HI) THEN Q_int(1 downto 0) <= "00"; ELSIF (en = HI) THEN Q_int(1 downto 0) <= D(1 downto 0); ELSE Q_int(1 downto 0) <= Q_int(1 downto 0); END IF; END IF; END PROCESS one; END behavioral; Test Bench for above code is as follows => LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY tb_Reg2 is -- testbench entity is ALWAYS EMPTY END tb_Reg2; ARCHITECTURE tb of tb_Reg2 is -- temporary signals SIGNAL clk_temp : std_logic := '0'; SIGNAL rst_temp, en_temp : std_logic := '0'; SIGNAL D_temp, Q_temp : std_logic_vector(1 downto 0):= "00"; -- component declaration COMPONENT Reg2 is PORT( clk, rst, en : IN std_logic; D : IN std_logic_vector(1 downto 0); Q : OUT std_logic_vector(1 downto 0) ); END COMPONENT; BEGIN UUT : Reg2 PORT MAP( clk => clk_temp, rst => rst_temp, en => en_temp, D => D_temp, Q => Q_temp ); -- Passing values to inputs clk_temp <= (not clk_temp) after 5 ns; rst_temp <= '0' after 0 ns, '1' after 3 ns, '0' after 15 ns; en_temp <= '1' after 5 ns,'0' after 36 ns; D_temp <= "10" after 4 ns, "01" after 16 ns, "11" after 32 ns, "00" after 55 ns; END tb; -- test bench ends
Reply by ●December 6, 20072007-12-06
>On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote: >> Anuja wrote: >> > assign Q = (rst==0)?Q_int:1'do; >> >> > How do i convert this to vhdl? I have to use a concurrent statementas>> >> Q <= Q_int when rst = '0' else '0'; > >Hi, > >I am having simulation problems with my code. I am trying to convert >Verilog code to VHDL. I can compile correctly. When i simulate the >following code in VHDL, value of Q_int is stuck at "00". It does not >change at all. Please let me know what the problem could be. >Remove the line: Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00"; after the BEGIN of the architecture.
Reply by ●December 6, 20072007-12-06
On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote:> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote: > >> Anuja wrote: > >> > assign Q = (rst==0)?Q_int:1'do; > > >> > How do i convert this to vhdl? I have to use a concurrent statement > as > > >> Q <= Q_int when rst = '0' else '0'; > > >Hi, > > >I am having simulation problems with my code. I am trying to convert > >Verilog code to VHDL. I can compile correctly. When i simulate the > >following code in VHDL, value of Q_int is stuck at "00". It does not > >change at all. Please let me know what the problem could be. > > Remove the line: > > Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00"; > > after the BEGIN of the architecture.- Hide quoted text - > > - Show quoted text -How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0; if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";
Reply by ●December 7, 20072007-12-07
>On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote: >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote: >> >> Anuja wrote: >> >> > assign Q = (rst==0)?Q_int:1'do; >> >> >> > How do i convert this to vhdl? I have to use a concurrentstatement>> as >> >> >> Q <= Q_int when rst = '0' else '0'; >> >> >Hi, >> >> >I am having simulation problems with my code. I am trying to convert >> >Verilog code to VHDL. I can compile correctly. When i simulate the >> >following code in VHDL, value of Q_int is stuck at "00". It does not >> >change at all. Please let me know what the problem could be. >> >> Remove the line: >> >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00"; >> >> after the BEGIN of the architecture.- Hide quoted text - >> >> - Show quoted text - > >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0; > >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else >"00"; >Sorry, my bad. I read your code too quickly, and thought you were assigning to Q in the clocked precess as well. Try: Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00"; Or better: Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);
Reply by ●December 7, 20072007-12-07
On Dec 7, 4:02 am, "RCIngham" <robert.ing...@gmail.com> wrote:> >On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote: > >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote: > >> >> Anuja wrote: > >> >> > assign Q = (rst==0)?Q_int:1'do; > > >> >> > How do i convert this to vhdl? I have to use a concurrent > statement > >> as > > >> >> Q <= Q_int when rst = '0' else '0'; > > >> >Hi, > > >> >I am having simulation problems with my code. I am trying to convert > >> >Verilog code to VHDL. I can compile correctly. When i simulate the > >> >following code in VHDL, value of Q_int is stuck at "00". It does not > >> >change at all. Please let me know what the problem could be. > > >> Remove the line: > > >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00"; > > >> after the BEGIN of the architecture.- Hide quoted text - > > >> - Show quoted text - > > >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0; > > >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else > >"00"; > > Sorry, my bad. I read your code too quickly, and thought you were > assigning to Q in the clocked precess as well. > > Try: > Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00"; > Or better: > Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);- Hide quoted text - > > - Show quoted text -neither one works. I am still having the same problem
Reply by ●December 7, 20072007-12-07
On Dec 4, 5:27 pm, Anuja <thakkar.an...@gmail.com> wrote:> Hello > > I am trying to convert the following code to vhdl > > assign Q = (rst==0)?Q_int:1'do; > > How do i convert this to vhdl? I have to use a concurrent statement as > this statement is not in the always block hence concurrent. I cannot > use an if then else statement as it is sequential. > > Please helpCould there be an issue with not having a "wait" at the bottom of your testbench process? Maybe that process is executing every delta cycle, with time never moving forward.
Reply by ●December 7, 20072007-12-07
On Dec 7, 9:44 am, Dave <dhsch...@gmail.com> wrote:> On Dec 4, 5:27 pm, Anuja <thakkar.an...@gmail.com> wrote: > > > Hello > > > I am trying to convert the following code to vhdl > > > assign Q = (rst==0)?Q_int:1'do; > > > How do i convert this to vhdl? I have to use a concurrent statement as > > this statement is not in the always block hence concurrent. I cannot > > use an if then else statement as it is sequential. > > > Please help > > Could there be an issue with not having a "wait" at the bottom of your > testbench process? Maybe that process is executing every delta cycle, > with time never moving forward.It maybe possible. Let me check on this and see what happens.
