Using Lattice ispLEVER with VHDL libraries

I am trying to pick up the Lattice ispLEVER tool and am having a bit
of trouble with it in regards to libraries.  I have several files for
the various libraries I have written for my VHDL.  In order to use
them, they have to be compiled in the correct order since some use
definitions from the others.  I can't seem to figure out how to tell
ispLEVER what order to compile the files.  It has a way to telling the
tool that a given file *is* a library, but that seems to be where it
stops.  I can't order the files in the project and it doesn't seem to
actually understand that the libraries exist in the VHDL.  I get
several error message all related to libraries not found or
identifiers not declared that should have been in the library files.

I have looked through every piece of documentation I can find and they
all pretty much gloss over the idea of user defined libraries.  Is
this something so simple I have missed it?

Did you include the use clause in your library package files that require 
dependancies? You can either reference the user defined library itself or 
just do: use work.my_package;

The error messages related to library not found is probably due to the 
library not being successfully compiled in the first place.

Colin


"rickman" <gnuarm@gmail.com> wrote in message 
news:284755cf-f23b-4979-9ecd-25d229fde921@e23g2000prf.googlegroups.com...
>I am trying to pick up the Lattice ispLEVER tool and am having a bit
> of trouble with it in regards to libraries.  I have several files for
> the various libraries I have written for my VHDL.  In order to use
> them, they have to be compiled in the correct order since some use
> definitions from the others.  I can't seem to figure out how to tell
> ispLEVER what order to compile the files.  It has a way to telling the
> tool that a given file *is* a library, but that seems to be where it
> stops.  I can't order the files in the project and it doesn't seem to
> actually understand that the libraries exist in the VHDL.  I get
> several error message all related to libraries not found or
> identifiers not declared that should have been in the library files.
>
> I have looked through every piece of documentation I can find and they
> all pretty much gloss over the idea of user defined libraries.  Is
> this something so simple I have missed it?
> 

Thanks for the reply.  No, that is not the problem.  The files compile
just fine under Modelsim and using the Altera tools.  In both of those
tools I can specify the order to compile the files.  These libraries
are files that I have my personal, common definitions and
conversions.  I know these files work because they have been used many
times before.

All I need to know is how the Lattice ispLever tool is told the order
to compile the files.


On Feb 19, 12:17 pm, "Colin Hankins" <Colin.Hank...@touit.com> wrote:
> Did you include the use clause in your library package files that require
> dependancies? You can either reference the user defined library itself or
> just do: use work.my_package;
>
> The error messages related to library not found is probably due to the
> library not being successfully compiled in the first place.
>
> Colin
>
> "rickman" <gnu...@gmail.com> wrote in message
>
> news:284755cf-f23b-4979-9ecd-25d229fde921@e23g2000prf.googlegroups.com...
>
> >I am trying to pick up the Lattice ispLEVER tool and am having a bit
> > of trouble with it in regards to libraries.  I have several files for
> > the various libraries I have written for my VHDL.  In order to use
> > them, they have to be compiled in the correct order since some use
> > definitions from the others.  I can't seem to figure out how to tell
> > ispLEVER what order to compile the files.  It has a way to telling the
> > tool that a given file *is* a library, but that seems to be where it
> > stops.  I can't order the files in the project and it doesn't seem to
> > actually understand that the libraries exist in the VHDL.  I get
> > several error message all related to libraries not found or
> > identifiers not declared that should have been in the library files.
>
> > I have looked through every piece of documentation I can find and they
> > all pretty much gloss over the idea of user defined libraries.  Is
> > this something so simple I have missed it?

No problem. The ispLever uses either Synplify or Precision to do the 
compilation. You will have to read about the tool you use to specify compile 
order. I use Precision and I believe you can not specify compile order. It 
will automatically determine it for you based on heirarchy and dependencies.

In making the move to ispLever, I had to add some extra use clauses to my 
user defined libraries to get things to go under ispLever. Because in my 
previous tools I could do a compile order but with Precision it looks for 
heirarchy and dependancy to set compile order.


"rickman" <gnuarm@gmail.com> wrote in message 
news:247a3be4-666e-433f-b6d6-08685b4df397@s37g2000prg.googlegroups.com...
> Thanks for the reply.  No, that is not the problem.  The files compile
> just fine under Modelsim and using the Altera tools.  In both of those
> tools I can specify the order to compile the files.  These libraries
> are files that I have my personal, common definitions and
> conversions.  I know these files work because they have been used many
> times before.
>
> All I need to know is how the Lattice ispLever tool is told the order
> to compile the files.
>
>
> On Feb 19, 12:17 pm, "Colin Hankins" <Colin.Hank...@touit.com> wrote:
>> Did you include the use clause in your library package files that require
>> dependancies? You can either reference the user defined library itself or
>> just do: use work.my_package;
>>
>> The error messages related to library not found is probably due to the
>> library not being successfully compiled in the first place.
>>
>> Colin
>>
>> "rickman" <gnu...@gmail.com> wrote in message
>>
>> news:284755cf-f23b-4979-9ecd-25d229fde921@e23g2000prf.googlegroups.com...
>>
>> >I am trying to pick up the Lattice ispLEVER tool and am having a bit
>> > of trouble with it in regards to libraries.  I have several files for
>> > the various libraries I have written for my VHDL.  In order to use
>> > them, they have to be compiled in the correct order since some use
>> > definitions from the others.  I can't seem to figure out how to tell
>> > ispLEVER what order to compile the files.  It has a way to telling the
>> > tool that a given file *is* a library, but that seems to be where it
>> > stops.  I can't order the files in the project and it doesn't seem to
>> > actually understand that the libraries exist in the VHDL.  I get
>> > several error message all related to libraries not found or
>> > identifiers not declared that should have been in the library files.
>>
>> > I have looked through every piece of documentation I can find and they
>> > all pretty much gloss over the idea of user defined libraries.  Is
>> > this something so simple I have missed it?
> 

Thanks for the reply.  I'm still not sure we are on the same page.  I
am trying to use ispLever as an IDE.  Yes, I am using Synplify for
synthesis, but I don't invoke it directly.  When I do invoke it
directly I can specify the compile order and it works ok.  The initial
response from the local FAE seems to be that I need to use an EDIT
tool flow and manually run the synthesis tool.  The initial response
from Lattice support is a canned message pointing me to a note totally
unrelated to my problem.

I am assuming there are some advantages to using the IDE rather than
using the tools as separate, unconnected programs.  If nothing else, I
expect it should make the setup simpler since I should only have to
set up the IDE and that will then handle the other tools.  Doesn't the
I in IDE stand for Integrated?

I also can't see to get Modelsim to work with ispLever, it seems they
don't license that with the starter kit.  So I will be using the
Altera or Xilinx tools to actually simulate my code and just use
ispLever to do the synthesis to generate a bit file, at least until I
make a final decision and buy the tools.

I only wish Xilinx had a part that would do the job, but they don't
seem to care much for putting FPGAs into small packages without using
BGAs.  Altera does have a part that will fit the socket, but it
doesn't have nearly as many LUTs as the Lattice part.

Which do you think would be easier, convincing Lattice to improve
their tools, or getting Xilinx to offer some Flash FPGAs in smaller
leaded packages?



On Feb 20, 1:14 pm, "Colin Hankins" <Colin.Hank...@touit.com> wrote:
> No problem. The ispLever uses either Synplify or Precision to do the
> compilation. You will have to read about the tool you use to specify compile
> order. I use Precision and I believe you can not specify compile order. It
> will automatically determine it for you based on heirarchy and dependencies.
>
> In making the move to ispLever, I had to add some extra use clauses to my
> user defined libraries to get things to go under ispLever. Because in my
> previous tools I could do a compile order but with Precision it looks for
> heirarchy and dependancy to set compile order.
>
> "rickman" <gnu...@gmail.com> wrote in message
>
> news:247a3be4-666e-433f-b6d6-08685b4df397@s37g2000prg.googlegroups.com...
>
> > Thanks for the reply.  No, that is not the problem.  The files compile
> > just fine under Modelsim and using the Altera tools.  In both of those
> > tools I can specify the order to compile the files.  These libraries
> > are files that I have my personal, common definitions and
> > conversions.  I know these files work because they have been used many
> > times before.
>
> > All I need to know is how the Lattice ispLever tool is told the order
> > to compile the files.
>
> > On Feb 19, 12:17 pm, "Colin Hankins" <Colin.Hank...@touit.com> wrote:
> >> Did you include the use clause in your library package files that require
> >> dependancies? You can either reference the user defined library itself or
> >> just do: use work.my_package;
>
> >> The error messages related to library not found is probably due to the
> >> library not being successfully compiled in the first place.
>
> >> Colin
>
> >> "rickman" <gnu...@gmail.com> wrote in message
>
> >>news:284755cf-f23b-4979-9ecd-25d229fde921@e23g2000prf.googlegroups.com...
>
> >> >I am trying to pick up the Lattice ispLEVER tool and am having a bit
> >> > of trouble with it in regards to libraries.  I have several files for
> >> > the various libraries I have written for my VHDL.  In order to use
> >> > them, they have to be compiled in the correct order since some use
> >> > definitions from the others.  I can't seem to figure out how to tell
> >> > ispLEVER what order to compile the files.  It has a way to telling the
> >> > tool that a given file *is* a library, but that seems to be where it
> >> > stops.  I can't order the files in the project and it doesn't seem to
> >> > actually understand that the libraries exist in the VHDL.  I get
> >> > several error message all related to libraries not found or
> >> > identifiers not declared that should have been in the library files.
>
> >> > I have looked through every piece of documentation I can find and they
> >> > all pretty much gloss over the idea of user defined libraries.  Is
> >> > this something so simple I have missed it?

rickman wrote:
> Thanks for the reply.  I'm still not sure we are on the same page.  I
> am trying to use ispLever as an IDE.  Yes, I am using Synplify for
> synthesis, but I don't invoke it directly.  When I do invoke it
> directly I can specify the compile order and it works ok.  

Then why not just batch this flow, that works ?

> The initial
> response from the local FAE seems to be that I need to use an EDIT
> tool flow and manually run the synthesis tool.

Which is what you describe above ?

>  The initial response
> from Lattice support is a canned message pointing me to a note totally
> unrelated to my problem.
> 
> I am assuming there are some advantages to using the IDE rather than
> using the tools as separate, unconnected programs.  If nothing else, I
> expect it should make the setup simpler since I should only have to
> set up the IDE and that will then handle the other tools.  Doesn't the
> I in IDE stand for Integrated?

Yes, but IDE's often fail on the details, and are tested on the
'first user' stuff.
The worst IDEs are the one's that do not allow external tool access :)

> 
> I also can't see to get Modelsim to work with ispLever, it seems they
> don't license that with the starter kit.  So I will be using the
> Altera or Xilinx tools to actually simulate my code and just use
> ispLever to do the synthesis to generate a bit file, at least until I
> make a final decision and buy the tools.
> 
> I only wish Xilinx had a part that would do the job, but they don't
> seem to care much for putting FPGAs into small packages without using
> BGAs.  Altera does have a part that will fit the socket, but it
> doesn't have nearly as many LUTs as the Lattice part.

I did see Actel have just released a QFN68 package, for their tiniest
FPGA (CPLD sized)

> 
> Which do you think would be easier, convincing Lattice to improve
> their tools, or getting Xilinx to offer some Flash FPGAs in smaller
> leaded packages?

That's easy - talk to Lattice :)
Give them an example, and convince them LOTS of users will
need to do (from the IDE) what you are trying to do.

-jg

rickman wrote:

> All I need to know is how the Lattice ispLever tool is told the order
> to compile the files.

http://www.latticesemi.com/products/designsoftware/isplever/ispleverstarter/index.cfm

Looks like you have the choice of Synplify or Precision.
Probably an ordered file list for these.
Check the docs.

            -- Mike Treseler

On Feb 21, 2:12 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
> rickman wrote:
> > All I need to know is how the Lattice ispLever tool is told the order
> > to compile the files.
>
> http://www.latticesemi.com/products/designsoftware/isplever/isplevers...
>
> Looks like you have the choice of Synplify or Precision.
> Probably an ordered file list for these.
> Check the docs.

Thanks for your reply. I had already stated that I could separately
invoke Synplify and get the files to compile.  I can't get it to work
using the Lattice IDE.  I contacted the local FAE and found out that
the new release from a couple of weeks ago fixes this so that user
libraries work correctly.  I just find it amazing that at this late
date such a simple feature was not working.  I wasn't told that it was
broken, I think they never supported user libraries until the latest
release.

rickman wrote:

> Thanks for your reply. I had already stated that I could separately
> invoke Synplify and get the files to compile.

Sorry, I missed that.

> I can't get it to work using the Lattice IDE.  

The device vendors all try to package their
collections of front and back end tools with
with a gui wrapper for demos and examples.

None of these stand up to serious use.
I am always better off doing the front end
and simulation from my favorite editor,
and the pin numbers and timing
with the place and route tool.

       -- Mike Treseler

Gents,

Saw this thread go by on my alert list and wanted to check in.

From the perspective of the synthesis and simulator, the Project
Navigator's job is to supply an ordered file list, command line flags,
and in some cases a script to automate a run.  There is no user-
defined file order 7.0. It will attempt to build an ordered file list
automatically. I have seen some VHDL designs fail under 7.0 that
requires Service Pack 2 to correct.

If all else fails, manage HDL source from within Synplify or Precision
and create an EDIF-based ispLEVER project.

It's accurate to say Project Navigator has some non-standard
conventions for HDL file management. I blame it partially because
system has a long history of managing all sorts of non-HDL file
formats like schematic, ABEL, and the native Lattice parameter
constraints file (LPC) created by IPexpress. Under the hood 7.0 is a
big improvement over 6.x, it has far better capacity, performance, and
language compliance when dealing with long file lists. It also
supports mixing VHDL and Verilog.

We are working on this area to make it closer to the conventions you'd
find in other EDA tools.

Troy Scott
Software Marketing
Lattice Semiconductor Corporation