BRAM synthesis question

Hi Peter, Symon, everyone,

Peter Alfke wrote:
> On Mar 11, 7:19 am, "Symon" <symon_bre...@hotmail.com> wrote:
>> Hi Paul,
>> Yeah, if you look at your code, you're trying to do an asynchronous read. I
>> suggest you try simulating your design and also a design where you
>> instantiate a block ram. You'll be able to compare and see clearly what the
>> block ram does.
> 
> This is not the first time that someone has tried to read the BRAM
> asynchronously. I have posted many times, and also inserted a sentence
> into our documentation that "nothing happens without a clock".
> Any ideas how we can spread this important (and non-obvious)
> information even better and wider???
> Peter Alfke, Xilinx Applications

My mistake was not realizing that - of course - the data on the BRAM are 
not available instantaneously, but will be available at the next clock 
cycle, hence the need to register them. I mistakenly thought 'hey, this 
process block has a clock in its sensitivity list, so why is XST still 
claiming I'm using it asynchronously?' So I was not "tryin to read the 
BRAM asynchronously" as Peter wonders, just not having any idea what I 
was doing ;-)

Thanks for the many helpful replies.

Regards. Paul Boven.

donald wrote:
(snip)

> This is an FPGA is it not.

> Nothing in an FPGA happens without a clock.

Where does this come from?  There is no reason one can't do
designs that don't use any FF's in an FPGA, though there is a
strong incentive to use them.

> Why would anyone think that BRAM would operate differently ??

Because that is the way traditional SRAMs work and people
get used to using them that way.  Also, most ROMs.

-- glen

job@amontec.com wrote:

> On Mar 11, 4:48 pm, Peter Alfke <pe...@xilinx.com> wrote:
(snip)

>>Any ideas how we can spread this important (and non-obvious)
>>information even better and wider???

> Just rename your component from BRAM to BSRAM ! Synchronous RAM !

Except that SRAM traditionally means Static RAM, so one might
still not notice.  How about BSyRAM?

-- glen

Peter Alfke wrote:
> On Mar 11, 7:19 am, "Symon" <symon_bre...@hotmail.com> wrote:
>> Hi Paul,
>> Yeah, if you look at your code, you're trying to do an asynchronous
>> read. I suggest you try simulating your design and also a design
>> where you instantiate a block ram. You'll be able to compare and see
>> clearly what the block ram does.
>> HTH., Syms.
>
> This is not the first time that someone has tried to read the BRAM
> asynchronously. I have posted many times, and also inserted a sentence
> into our documentation that "nothing happens without a clock".
> Any ideas how we can spread this important (and non-obvious)
> information even better and wider???
> Peter Alfke, Xilinx Applications

Hi Peter,
When the synthesis software itself warns the user "The RAM <XYZ> will be 
implemented on LUTs because you have described an asynchronous read" and 
they still don't get it, I'm struggling to see what would be of further 
help?
Cheers, Syms. 

Mike Treseler <mike_treseler@comcast.net> wrote:
> If I worked for Xilinx I would write an
> ap note in vhdl and verilog for a useful
> application example that infers block ram from code,
> and then reference that example in all related documents.

	it's all (public) available:

	- XAPP463 ("Using BRAMs in Spartan-3 FPGA") applies also for 
virtex-2 and with some additions/modifications for the newer virtex 
parts.

	- In the xilinx "synthesis and simulation guide" chapter 4,
page 152 pp, there are some (usefull) generic HDL code examples: How 
to implement a "generic BRAM" in VHDL and/or verilog. 

WD
--