DDR3 speed, Altera vs Xilinx

On Mar 14, 8:24=A0am, austin <aus...@xilinx.com> wrote:
> Morten,
>
> We chose different paths: =A0Altera used hardened logic to get their
> speed, where we chose to stay general, and use any pins/any fabric/any
> standard.
>
> We have DDR3 designs that are also working at 533 MHz.
>
> Best to sit down and talk with your FAE on the subject.
>
> There are many other factors to consider (not he least of which is we
> are in full production on Virtex 5 LX, LXT, SXT, and they are just now
> in ES on on few parts, with S3 GX canceled completely).
>
> Even though Altera has some really mean, cool, and neat power point
> presentations, we basically have no competition whatsoever at 65nm at
> the high end (as you can't ship power point in your systems).
>
> Austin

While Virtex 5 has indeed been shipping longer and is a very strong
product, Stratix III FPGAs are shipping and doing well. Altera ships
production qualified Stratix III FPGAs this week and has rolled out
multiple devices.

Our customers have highlighted they like the sizable density
advantages of the biggest FPGA, the 3SL340 device (>15% higher LE
count, 35% more flip-flops, 60% more memory, 3X DSP resources).
Other customers like the clear performance advantages (2x speed grade
edge).
Others like the compile time advantage (1/3 the compile time to get
far higher utilization).
Still others like the power benefits (30% lower power validated on
silicon).
And others like the working 533 MHz DDR3 solution that also supports
DIMMs.

Stratix II GX continues to be the optimal solution for customers
requiring transceiver performance >3.75 Gbps, though Virtex 5 LXT is
indeed a very strong product for slower speed designs.

Please contact your Altera rep for further details on any of the
products above. We also have some very nice PowerPoint presentations.

Dave Greenfield
Altera Product Marketing

On 17 Mrz., 07:00, Dave Greenfield <dav...@altera.com> wrote:
> On Mar 14, 8:24 am, austin <aus...@xilinx.com> wrote:
>
>
>
> > Morten,
>
> > We chose different paths:  Altera used hardened logic to get their
> > speed, where we chose to stay general, and use any pins/any fabric/any
> > standard.
>
> > We have DDR3 designs that are also working at 533 MHz.
>
> > Best to sit down and talk with your FAE on the subject.
>
> > There are many other factors to consider (not he least of which is we
> > are in full production on Virtex 5 LX, LXT, SXT, and they are just now
> > in ES on on few parts, with S3 GX canceled completely).
>
> > Even though Altera has some really mean, cool, and neat power point
> > presentations, we basically have no competition whatsoever at 65nm at
> > the high end (as you can't ship power point in your systems).
>
> > Austin
>
> While Virtex 5 has indeed been shipping longer and is a very strong
> product, Stratix III FPGAs are shipping and doing well. Altera ships
> production qualified Stratix III FPGAs this week and has rolled out
> multiple devices.
>
> Our customers have highlighted they like the sizable density
> advantages of the biggest FPGA, the 3SL340 device (>15% higher LE
> count, 35% more flip-flops, 60% more memory, 3X DSP resources).
> Other customers like the clear performance advantages (2x speed grade
> edge).
> Others like the compile time advantage (1/3 the compile time to get
> far higher utilization).
> Still others like the power benefits (30% lower power validated on
> silicon).
> And others like the working 533 MHz DDR3 solution that also supports
> DIMMs.
>
> Stratix II GX continues to be the optimal solution for customers
> requiring transceiver performance >3.75 Gbps, though Virtex 5 LXT is
> indeed a very strong product for slower speed designs.
>
> Please contact your Altera rep for further details on any of the
> products above. We also have some very nice PowerPoint presentations.
>
> Dave Greenfield
> Altera Product Marketing

hiphip hurraa..!

V5 is nice product for lower speed designs ;) eh, but seriously there
are companies
who make BIG promises and decrease the real numbers, so has MGT
performance
gradually decreased while technology advanced V2ProX -> V4 -> V5,
Lattice as example hasnt ever promised MGT speeds higher then they are
able
to deliver, they say that they can do up to 3.6G, hmmm...

quote "SIIGX continues"... it does actually confirm the statement from
Xilinx
that SIII-GX is cancelled. So maybe Altera has also problems above
3.6G with SIII-GX, so it isnt even offered, forcing the MGT user to
use one
family older silicon ?

Ok, whatever Altera has at the moment (compared to Xilinx)
a) better package options for low cost families
b) better offers and package options for CPLD (MAX2/Z)

This is something Xilinx CAN NOT DENY. Maybe the think
flexible small form factor package options are not important for
consumer market. Maybe.

And maybe Xilinx is trying to get out from CPLD business. Maybe.

If not then its pretty much time to offer low cost small factor
FPGAs and something new for CPLD-like desings for Xilinx.

Or maybe increase MGT speed to >6G for Virtex-6 ?
Eh even V5FXT isnt officially released. Maybe Xilinx is so busy
doing the RAD-hardening for V5, its still hard task and they only
got 23M$ contract todo this. Eh hope the rad-hardening of V5
doesnt add any other delay into the release of normal V5

Antti

Austin,

Thanks for your reply. I know this is kinda flamebait for you and your 
competitor, and I will review all postings with care.

I have put my xilinx dealer to the work of finding real solution (not 
powerpoints, or postings on this site ;)) working at high speed. I don't 
really think we will get to 533Mhz, but want to compare REAL performance. 
For our upcoming design DDR speed and IO count is the main criterias for 
selection.

A 32bit design is of no help for me. Altera claims to have 12 dedicated DQS 
pins on every side, where 2 sides can run at 533Mhz on their fastest device 
(wich is theoretically 216 pins when using 9bit ECC mem) . They claim to 
have 72bit real hw proving this, and Im waiting to see how this is done. For 
Xilinx, I have no idea how wide bus they can do. I've only seen 64bit 
designs at much lower rate for now. I am hoping they(you?) can show me 
something better.

I know there is a lot of the "marketing numbers" out there and my colleagues 
have wide experience on trying to achive "marketing" numbers (and even got 
the supplier convinced that their numbers didn't work).

Because of this, I need to see a working design before aiming at any number.

Best regards,
Morten

"austin" <austin@xilinx.com> wrote in message 
news:fre5b8$71c1@cnn.xsj.xilinx.com...
> Morten,
>
> We chose different paths:  Altera used hardened logic to get their
> speed, where we chose to stay general, and use any pins/any fabric/any
> standard.
>
> We have DDR3 designs that are also working at 533 MHz.
>
> Best to sit down and talk with your FAE on the subject.
>
> There are many other factors to consider (not he least of which is we
> are in full production on Virtex 5 LX, LXT, SXT, and they are just now
> in ES on on few parts, with S3 GX canceled completely).
>
> Even though Altera has some really mean, cool, and neat power point
> presentations, we basically have no competition whatsoever at 65nm at
> the high end (as you can't ship power point in your systems).
>
> Austin 

Me too.
I need to stream 60 Bits at 833MHz in our next project to a large RAM,
so depending on controller overhead
something like 64 bit at 500MHz DDR would be a good thing to have.

Kolja Sulimma

On 17 Mrz., 10:10, "Morten Leikvoll" <mleik...@yajoo.nospam> wrote:
> Austin,
> For
> Xilinx, I have no idea how wide bus they can do. I've only seen 64bit
> designs at much lower rate for now. I am hoping they(you?) can show me
> something better.
>

> Because of this, I need to see a working design before aiming at any number.

> "austin" <aus...@xilinx.com> wrote in message
> > We have DDR3 designs that are also working at 533 MHz.

Morten,

Like I advised, you need to get your local FAE in to see you.  We have
demo boards for memory, networking, PCI Express, etc. so it is not hard
to see what we actually sell as a "realization" of our claims.

http://www.xilinx.com/products/devkits/HW-V5-ML561-UNI-G.htm
(memory pcb for V5)
http://www.xilinx.com/products/devkits/HW-V5-ML555-G.htm
(PCIe pcb for V5)
...

Can you do better than we do on our own demo pcb's?  Yes, you can, but
that does require more work.

The memory interface generator (MIG) is designed to "solve" the problems
(not create new ones), so it is, by its very nature, conservative.  What
is more important: specifying your memory and pressing a button and
generating a working design, or starting from scratch and squeezing the
best performance possible out of the interface?  Your choice, we will
support you.

Since our solution in V5 is still general (no hardened features for
DDR3), the bus width is whatever you wish.  I know of customers who use
288 bit wide bus, as that is 4 X 72, and 72 is the width needed to take
advantage of the ECC block which can be used with your external memory
(for error check and correct).

I won't waste your time talking about Altera. Having their FAE visit
you, and show you their solutions, is another necessary part of the work
ahead of you.

Then, you decide.

I may be having fun right now due to Altera's 65nm misfortune, but I am
a realist, too, and I know they will "be baaack!"

Austin

Antti wrote:
> I used PIC when PIC15C54 was "hot", as they had almost
> no competition. I changed to AVR as they are better.

Better for some things, not for everything.  I had several designs using
PICs for which AVRs would not have been fast enough.  (There are faster
AVRs now, but there are faster PICs too.)

If one were to pick parts purely on technical merit of the parts, both
would win some designs.  However, there's also the tradeoff of saving
development time by using parts and tools with which one is already
experienced.

On 18 Mrz., 01:11, Eric Smith <e...@brouhaha.com> wrote:
> Antti wrote:
> > I used PIC when PIC15C54 was "hot", as they had almost
> > no competition. I changed to AVR as they are better.
>
> Better for some things, not for everything.  I had several designs using
> PICs for which AVRs would not have been fast enough.  (There are faster
> AVRs now, but there are faster PICs too.)
>
> If one were to pick parts purely on technical merit of the parts, both
> would win some designs.  However, there's also the tradeoff of saving
> development time by using parts and tools with which one is already
> experienced.

yes agreed, at the beginning where it was PIC16C84 vs AT90S1200
it was clear win for AVR, but microchip has no so many new chips
that they defenetly win designs where AVR do not fit because of
lack of functions or speed or other details.

well both PIC and AVRs are no loosing against 32 bit low cost MCUs
eh, I am writing just now "My first STM32" book ;) a ARM that cost
less 3 usd runs at 72mhz (also from internal osc!) and has USB
and 64KByte flash.. why think of 8 bit micros for designs where
the 3 usd price is acceptable? sure for sub 1 usd prices 8 bit
MCUs are considered.

Antti

Austin,

Thanks for the information.
The ML561 board immediately caught my attention as it seem to support 
2x72pin dimms in ddr2 at 333Mhz on a VLX50T -2, but the docs refer to 
xapp850, wich at the moment has a dead link and is nowhere else to find. 
Maybe you can direct me to that?

This is a documented number I can relate to :) Also I would guess this 
design looses a bit of speed as it has some empty x16 simms disturbing many 
of the signals.

I know all the external stuff needed to improve speed, but I have little 
detailed control of the internals. Some of the internals can be very hard to 
get to (like IO skew, delays (to ball), ripple and so on). Often we need to 
know this to tweak max performance. We need to handle the setup/hold times 
from the datasheet as a sum of all these unknown parameters, and they may 
not add up.

Thanks again,
Morten

On Mar 18, 6:44 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
> Austin,
>
> Thanks for the information.
> The ML561 board immediately caught my attention as it seem to support
> 2x72pin dimms in ddr2 at 333Mhz on a VLX50T -2, but the docs refer to
> xapp850, wich at the moment has a dead link and is nowhere else to find.
> Maybe you can direct me to that?
>
> This is a documented number I can relate to :) Also I would guess this
> design looses a bit of speed as it has some empty x16 simms disturbing many
> of the signals.
>
> I know all the external stuff needed to improve speed, but I have little
> detailed control of the internals. Some of the internals can be very hard to
> get to (like IO skew, delays (to ball), ripple and so on). Often we need to
> know this to tweak max performance. We need to handle the setup/hold times
> from the datasheet as a sum of all these unknown parameters, and they may
> not add up.
>
> Thanks again,
> Morten

Check out the Altera StratixIII for DDR3 speeds.
There is a video demo on the front page that shows it up to 1.067Gbps.
Not sure if Xilinx can touch that?
http://www.altera.com/b/stratixiii-ddr3-video.html