NVRAM design in CPLD

Hi all,

For the ram implied in a CPLD design, will the data written in it
remain after power off?

I have a small rom in my curent CPLD design, occasionally I need
change the content inside, instead of reprogramming it, I want
something like a nvram that I can update through the uP dynamicallly.

Thanks,
Jay

jay wrote:
> Hi all,
> 
> For the ram implied in a CPLD design, will the data written in it
> remain after power off?
> 
> I have a small rom in my curent CPLD design, occasionally I need
> change the content inside, instead of reprogramming it, I want
> something like a nvram that I can update through the uP dynamicallly.

That depends on the CPLD.
Some do have a mode, where you can load the CPLD config
latches and not the NV_Fuse_memory.
(I think Atmel ATF15xxBE series have the twin modes)

not sure of the details, ie when the change-over occurs
and what the pins do during re-load

-jg

On 6=D4=C227=C8=D5, =CF=C2=CE=E71=CA=B152=B7=D6, Jim Granville <no.s...@des=
igntools.maps.co.nz>
wrote:
> jay wrote:
> > Hi all,
>
> > For the ram implied in a CPLD design, will the data written in it
> > remain after power off?
>
> > I have a small rom in my curent CPLD design, occasionally I need
> > change the content inside, instead of reprogramming it, I want
> > something like a nvram that I can update through the uP dynamicallly.
>
> That depends on the CPLD.
> Some do have a mode, where you can load the CPLD config
> latches and not the NV_Fuse_memory.
> (I think Atmel ATF15xxBE series have the twin modes)
>
> not sure of the details, ie when the change-over occurs
> and what the pins do during re-load
>
> -jg

Thanks, but I'm only using a general CPLD from A.

Jay

On Jun 27, 2:19 am, jay <heavenf...@gmail.com> wrote:
> On 6=D4=C227=C8=D5, =CF=C2=CE=E71=CA=B152=B7=D6, Jim Granville <no.s...@d=
esigntools.maps.co.nz>
> wrote:
>
>
>
> > jay wrote:
> > > Hi all,
>
> > > For the ram implied in a CPLD design, will the data written in it
> > > remain after power off?
>
> > > I have a small rom in my curent CPLD design, occasionally I need
> > > change the content inside, instead of reprogramming it, I want
> > > something like a nvram that I can update through the uP dynamicallly.
>
> > That depends on the CPLD.
> > Some do have a mode, where you can load the CPLD config
> > latches and not the NV_Fuse_memory.
> > (I think Atmel ATF15xxBE series have the twin modes)
>
> > not sure of the details, ie when the change-over occurs
> > and what the pins do during re-load
>
> > -jg
>
> Thanks, but I'm only using a general CPLD from A.
>
> Jay

If you can't switch the CPLD for another PLD, I'm afraid you'll have
to reprogram the device as a whole to do this. If you are open to
change though, in Lattice XP2 FPGA (which are flash based -so system-
wise they're very close to big CPLDs) there is a relatively small
flash memory (TAG memory) with an external (and internal) SPI
interface. The TAG memory can be reprogrammed while these device are
operating.
Alex