Forums

FPGA/DSP Expert - business partner for innovative FFT

Started by Seung August 13, 2003
Hello

I have a patent and recently added one more on innovative FFT
algorithm and architecture.
If you're a business minded expert on FPGA with interests in DSP, this
is a great opportunity. Our FFT is 'the' optimal HW solution as
follows:

1. Minimum HW complexity: 100% HW utilization
2. Suitable for super fast pipelined FFT: only local data flow - not
based on butterfly algorithm
3. Minimum clock cycles: baseline architecture needs N clock for
N-point FFT
4. Scalable to arbitrary large FFT size
5. Multi-dimension extension: world's first 'intrinsic'
multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs)
: great for 2-D/3-D real-time medical imaging, SAR, etc.

If you're interested in building a business together based on this
innovation,
please contact me with your resume. It'll be ideal if you have
contacts for potential customers.

Any help on this matter from FPGA/DSP group members will be
appreciated.


Thanks.

Seung P. Kim, Ph.D
Silicon Computing, Inc.
Mountain View, CA
Hello Seung,

If you have 100% hardware utilization, doesn't this present a problem if you
make a change to the design??

Curious what is the # for your patent??

Clay




"Seung" <kim.seung@sbcglobal.net> wrote in message
news:fdf92243.0308131136.74aff961@posting.google.com...
> Hello > > I have a patent and recently added one more on innovative FFT > algorithm and architecture. > If you're a business minded expert on FPGA with interests in DSP, this > is a great opportunity. Our FFT is 'the' optimal HW solution as > follows: > > 1. Minimum HW complexity: 100% HW utilization > 2. Suitable for super fast pipelined FFT: only local data flow - not > based on butterfly algorithm > 3. Minimum clock cycles: baseline architecture needs N clock for > N-point FFT > 4. Scalable to arbitrary large FFT size > 5. Multi-dimension extension: world's first 'intrinsic' > multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs) > : great for 2-D/3-D real-time medical imaging, SAR, etc. > > If you're interested in building a business together based on this > innovation, > please contact me with your resume. It'll be ideal if you have > contacts for potential customers. > > Any help on this matter from FPGA/DSP group members will be > appreciated. > > > Thanks. > > Seung P. Kim, Ph.D > Silicon Computing, Inc. > Mountain View, CA
Hi Clay,

Not at all. You just need to add more stages.
My first patent on this is US5528736. The following patent number
is to be issued within three months.
If you are interested in more details, please send me an e-mail.

Regards,

Seung


"Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message news:<sVw_a.7804$_3.5732@fe02.atl2.webusenet.com>...
> Hello Seung, > > If you have 100% hardware utilization, doesn't this present a problem if you > make a change to the design?? > > Curious what is the # for your patent?? > > Clay > > > > > "Seung" <kim.seung@sbcglobal.net> wrote in message > news:fdf92243.0308131136.74aff961@posting.google.com... > > Hello > > > > I have a patent and recently added one more on innovative FFT > > algorithm and architecture. > > If you're a business minded expert on FPGA with interests in DSP, this > > is a great opportunity. Our FFT is 'the' optimal HW solution as > > follows: > > > > 1. Minimum HW complexity: 100% HW utilization > > 2. Suitable for super fast pipelined FFT: only local data flow - not > > based on butterfly algorithm > > 3. Minimum clock cycles: baseline architecture needs N clock for > > N-point FFT > > 4. Scalable to arbitrary large FFT size > > 5. Multi-dimension extension: world's first 'intrinsic' > > multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs) > > : great for 2-D/3-D real-time medical imaging, SAR, etc. > > > > If you're interested in building a business together based on this > > innovation, > > please contact me with your resume. It'll be ideal if you have > > contacts for potential customers. > > > > Any help on this matter from FPGA/DSP group members will be > > appreciated. > > > > > > Thanks. > > > > Seung P. Kim, Ph.D > > Silicon Computing, Inc. > > Mountain View, CA
You can find the patent here:
http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1
&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=5528736.WKU.&OS=PN/5528736&RS=PN/55
28736
(Watch the word wrap--I wish I knew how to get shorter URLs out of the USPTO
site.)

Clay, I interpreted his statement about "100% HW utilization" to mean that
it packed well into current FPGA architectures, allowing (near) 100%
utilization of the FPGA, not that it required 100% of any particular HW
device.

-Jon

"Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message
news:sVw_a.7804$_3.5732@fe02.atl2.webusenet.com...
> Hello Seung, > > If you have 100% hardware utilization, doesn't this present a problem if
you
> make a change to the design?? > > Curious what is the # for your patent?? > > Clay > > > "Seung" <kim.seung@sbcglobal.net> wrote in message > news:fdf92243.0308131136.74aff961@posting.google.com... > > Hello > > > > I have a patent and recently added one more on innovative FFT > > algorithm and architecture. > > If you're a business minded expert on FPGA with interests in DSP, this > > is a great opportunity. Our FFT is 'the' optimal HW solution as > > follows: > > > > 1. Minimum HW complexity: 100% HW utilization > > 2. Suitable for super fast pipelined FFT: only local data flow - not > > based on butterfly algorithm > > 3. Minimum clock cycles: baseline architecture needs N clock for > > N-point FFT > > 4. Scalable to arbitrary large FFT size > > 5. Multi-dimension extension: world's first 'intrinsic' > > multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs) > > : great for 2-D/3-D real-time medical imaging, SAR, etc. > > > > If you're interested in building a business together based on this > > innovation, > > please contact me with your resume. It'll be ideal if you have > > contacts for potential customers. > > > > Any help on this matter from FPGA/DSP group members will be > > appreciated. > > > > > > Thanks. > > > > Seung P. Kim, Ph.D > > Silicon Computing, Inc. > > Mountain View, CA > > >
Jon

This will be your friend for long URLs.
http://tinyurl.com/
You can create a toolbar button and click that after a long link web page
and it voila, out pops the smaller one.
For example...
http://tinyurl.com/k1x6

Cheers
Bhaskar

"Jon Harris" <jon_harrisTIGER@hotmail.com> wrote in message
news:3f3a9180$1_1@newsfeed...
> You can find the patent here: >
http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1
>
&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=5528736.WKU.&OS=PN/5528736&RS=PN/55
> 28736 > (Watch the word wrap--I wish I knew how to get shorter URLs out of the
USPTO
> site.) > > Clay, I interpreted his statement about "100% HW utilization" to mean that > it packed well into current FPGA architectures, allowing (near) 100% > utilization of the FPGA, not that it required 100% of any particular HW > device. > > -Jon > > "Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message > news:sVw_a.7804$_3.5732@fe02.atl2.webusenet.com... > > Hello Seung, > > > > If you have 100% hardware utilization, doesn't this present a problem if > you > > make a change to the design?? > > > > Curious what is the # for your patent?? > > > > Clay > > > > > > "Seung" <kim.seung@sbcglobal.net> wrote in message > > news:fdf92243.0308131136.74aff961@posting.google.com... > > > Hello > > > > > > I have a patent and recently added one more on innovative FFT > > > algorithm and architecture. > > > If you're a business minded expert on FPGA with interests in DSP, this > > > is a great opportunity. Our FFT is 'the' optimal HW solution as > > > follows: > > > > > > 1. Minimum HW complexity: 100% HW utilization > > > 2. Suitable for super fast pipelined FFT: only local data flow - not > > > based on butterfly algorithm > > > 3. Minimum clock cycles: baseline architecture needs N clock for > > > N-point FFT > > > 4. Scalable to arbitrary large FFT size > > > 5. Multi-dimension extension: world's first 'intrinsic' > > > multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs) > > > : great for 2-D/3-D real-time medical imaging, SAR, etc. > > > > > > If you're interested in building a business together based on this > > > innovation, > > > please contact me with your resume. It'll be ideal if you have > > > contacts for potential customers. > > > > > > Any help on this matter from FPGA/DSP group members will be > > > appreciated. > > > > > > > > > Thanks. > > > > > > Seung P. Kim, Ph.D > > > Silicon Computing, Inc. > > > Mountain View, CA > > > > > > > >
That toolbar method is pretty neat!  The only thing I wonder about is how
long the URL redirection will work.  And of course it assumes that the
tinyURL server is always up.

"Bhaskar Thiagarajan" <bhaskart@deja.com> wrote in message
news:bhgrnu$lln6$1@ID-82263.news.uni-berlin.de...
> Jon > > This will be your friend for long URLs. > http://tinyurl.com/ > You can create a toolbar button and click that after a long link web page > and it voila, out pops the smaller one. > For example... > http://tinyurl.com/k1x6 > > Cheers > Bhaskar > > "Jon Harris" <jon_harrisTIGER@hotmail.com> wrote in message > news:3f3a9180$1_1@newsfeed... > > You can find the patent here: > > >
http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1
> > >
&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=5528736.WKU.&OS=PN/5528736&RS=PN/55
> > 28736 > > (Watch the word wrap--I wish I knew how to get shorter URLs out of the > USPTO > > site.) > > > > Clay, I interpreted his statement about "100% HW utilization" to mean
that
> > it packed well into current FPGA architectures, allowing (near) 100% > > utilization of the FPGA, not that it required 100% of any particular HW > > device. > > > > -Jon > > > > "Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message > > news:sVw_a.7804$_3.5732@fe02.atl2.webusenet.com... > > > Hello Seung, > > > > > > If you have 100% hardware utilization, doesn't this present a problem
if
> > you > > > make a change to the design?? > > > > > > Curious what is the # for your patent?? > > > > > > Clay > > > > > > > > > "Seung" <kim.seung@sbcglobal.net> wrote in message > > > news:fdf92243.0308131136.74aff961@posting.google.com... > > > > Hello > > > > > > > > I have a patent and recently added one more on innovative FFT > > > > algorithm and architecture. > > > > If you're a business minded expert on FPGA with interests in DSP,
this
> > > > is a great opportunity. Our FFT is 'the' optimal HW solution as > > > > follows: > > > > > > > > 1. Minimum HW complexity: 100% HW utilization > > > > 2. Suitable for super fast pipelined FFT: only local data flow - not > > > > based on butterfly algorithm > > > > 3. Minimum clock cycles: baseline architecture needs N clock for > > > > N-point FFT > > > > 4. Scalable to arbitrary large FFT size > > > > 5. Multi-dimension extension: world's first 'intrinsic' > > > > multi-dimensional FFT algorithm & architecture (not relay on 1-D
FFTs)
> > > > : great for 2-D/3-D real-time medical imaging, SAR, etc. > > > > > > > > If you're interested in building a business together based on this > > > > innovation, > > > > please contact me with your resume. It'll be ideal if you have > > > > contacts for potential customers. > > > > > > > > Any help on this matter from FPGA/DSP group members will be > > > > appreciated. > > > > > > > > > > > > Thanks. > > > > > > > > Seung P. Kim, Ph.D > > > > Silicon Computing, Inc. > > > > Mountain View, CA > > > > > > > > > > > > > > >
Hi Jon and Clay,

I used the phrase '100% HW utilization' as an indicator of how well 
the HW matches with the algorithm (as old systolic architecture guys
would
use the term) -  it means no hardware is wasted sitting idle. So it is
not meant for FPGA utilization percentage, but rather usage
indicator of synthesized logic.

Regards,

Seung




"Jon Harris" <jon_harrisTIGER@hotmail.com> wrote in message news:<3f3a9180$1_1@newsfeed>...
> You can find the patent here: > http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1 > &u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=5528736.WKU.&OS=PN/5528736&RS=PN/55 > 28736 > (Watch the word wrap--I wish I knew how to get shorter URLs out of the USPTO > site.) > > Clay, I interpreted his statement about "100% HW utilization" to mean that > it packed well into current FPGA architectures, allowing (near) 100% > utilization of the FPGA, not that it required 100% of any particular HW > device. > > -Jon > > "Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message > news:sVw_a.7804$_3.5732@fe02.atl2.webusenet.com... > > Hello Seung, > > > > If you have 100% hardware utilization, doesn't this present a problem if > you > > make a change to the design?? > > > > Curious what is the # for your patent?? > > > > Clay > > > > > > "Seung" <kim.seung@sbcglobal.net> wrote in message > > news:fdf92243.0308131136.74aff961@posting.google.com... > > > Hello > > > > > > I have a patent and recently added one more on innovative FFT > > > algorithm and architecture. > > > If you're a business minded expert on FPGA with interests in DSP, this > > > is a great opportunity. Our FFT is 'the' optimal HW solution as > > > follows: > > > > > > 1. Minimum HW complexity: 100% HW utilization > > > 2. Suitable for super fast pipelined FFT: only local data flow - not > > > based on butterfly algorithm > > > 3. Minimum clock cycles: baseline architecture needs N clock for > > > N-point FFT > > > 4. Scalable to arbitrary large FFT size > > > 5. Multi-dimension extension: world's first 'intrinsic' > > > multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs) > > > : great for 2-D/3-D real-time medical imaging, SAR, etc. > > > > > > If you're interested in building a business together based on this > > > innovation, > > > please contact me with your resume. It'll be ideal if you have > > > contacts for potential customers. > > > > > > Any help on this matter from FPGA/DSP group members will be > > > appreciated. > > > > > > > > > Thanks. > > > > > > Seung P. Kim, Ph.D > > > Silicon Computing, Inc. > > > Mountain View, CA > > > > > >
I've only been using this for a few months now. So it's hard to say. Perhaps
not that reliable for getting archived in Google groups, but then, even a
full link doesn't seem to stand the test of time these days. I have to
constantly delete or modify my bookmarks folder for broken links.

"Jon Harris" <jon_harrisTIGER@hotmail.com> wrote in message
news:3f3ad2ce$1_1@newsfeed...
> That toolbar method is pretty neat! The only thing I wonder about is how > long the URL redirection will work. And of course it assumes that the > tinyURL server is always up. > > "Bhaskar Thiagarajan" <bhaskart@deja.com> wrote in message > news:bhgrnu$lln6$1@ID-82263.news.uni-berlin.de... > > Jon > > > > This will be your friend for long URLs. > > http://tinyurl.com/ > > You can create a toolbar button and click that after a long link web
page
> > and it voila, out pops the smaller one. > > For example... > > http://tinyurl.com/k1x6 > > > > Cheers > > Bhaskar > > > > "Jon Harris" <jon_harrisTIGER@hotmail.com> wrote in message > > news:3f3a9180$1_1@newsfeed... > > > You can find the patent here: > > > > > >
http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1
> > > > > >
&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=5528736.WKU.&OS=PN/5528736&RS=PN/55
> > > 28736 > > > (Watch the word wrap--I wish I knew how to get shorter URLs out of the > > USPTO > > > site.) > > > > > > Clay, I interpreted his statement about "100% HW utilization" to mean > that > > > it packed well into current FPGA architectures, allowing (near) 100% > > > utilization of the FPGA, not that it required 100% of any particular
HW
> > > device. > > > > > > -Jon > > > > > > "Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in
message
> > > news:sVw_a.7804$_3.5732@fe02.atl2.webusenet.com... > > > > Hello Seung, > > > > > > > > If you have 100% hardware utilization, doesn't this present a
problem
> if > > > you > > > > make a change to the design?? > > > > > > > > Curious what is the # for your patent?? > > > > > > > > Clay > > > > > > > > > > > > "Seung" <kim.seung@sbcglobal.net> wrote in message > > > > news:fdf92243.0308131136.74aff961@posting.google.com... > > > > > Hello > > > > > > > > > > I have a patent and recently added one more on innovative FFT > > > > > algorithm and architecture. > > > > > If you're a business minded expert on FPGA with interests in DSP, > this > > > > > is a great opportunity. Our FFT is 'the' optimal HW solution as > > > > > follows: > > > > > > > > > > 1. Minimum HW complexity: 100% HW utilization > > > > > 2. Suitable for super fast pipelined FFT: only local data flow -
not
> > > > > based on butterfly algorithm > > > > > 3. Minimum clock cycles: baseline architecture needs N clock for > > > > > N-point FFT > > > > > 4. Scalable to arbitrary large FFT size > > > > > 5. Multi-dimension extension: world's first 'intrinsic' > > > > > multi-dimensional FFT algorithm & architecture (not relay on 1-D > FFTs) > > > > > : great for 2-D/3-D real-time medical imaging, SAR, etc. > > > > > > > > > > If you're interested in building a business together based on this > > > > > innovation, > > > > > please contact me with your resume. It'll be ideal if you have > > > > > contacts for potential customers. > > > > > > > > > > Any help on this matter from FPGA/DSP group members will be > > > > > appreciated. > > > > > > > > > > > > > > > Thanks. > > > > > > > > > > Seung P. Kim, Ph.D > > > > > Silicon Computing, Inc. > > > > > Mountain View, CA > > > > > > > > > > > > > > > > > > > > > > > >
"Jon Harris" <jon_harrisTIGER@hotmail.com> wrote in message news:<3f3a9180$1_1@newsfeed>...
> You can find the patent here: > http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1 > &u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=5528736.WKU.&OS=PN/5528736&RS=PN/55 > 28736 > (Watch the word wrap--I wish I knew how to get shorter URLs out of the USPTO > site.) >
Try www.tinyurl.com With that utility, the url became: http://tinyurl.com/k1x6
> Clay, I interpreted his statement about "100% HW utilization" to mean that > it packed well into current FPGA architectures, allowing (near) 100% > utilization of the FPGA, not that it required 100% of any particular HW > device. > > -Jon > > "Clay S. Turner" <physicsNOOOOSPPPPAMMMM@bellsouth.net> wrote in message > news:sVw_a.7804$_3.5732@fe02.atl2.webusenet.com... > > Hello Seung, > > > > If you have 100% hardware utilization, doesn't this present a problem if > you > > make a change to the design?? > > > > Curious what is the # for your patent?? > > > > Clay > > > > > > "Seung" <kim.seung@sbcglobal.net> wrote in message > > news:fdf92243.0308131136.74aff961@posting.google.com... > > > Hello > > > > > > I have a patent and recently added one more on innovative FFT > > > algorithm and architecture. > > > If you're a business minded expert on FPGA with interests in DSP, this > > > is a great opportunity. Our FFT is 'the' optimal HW solution as > > > follows: > > > > > > 1. Minimum HW complexity: 100% HW utilization > > > 2. Suitable for super fast pipelined FFT: only local data flow - not > > > based on butterfly algorithm > > > 3. Minimum clock cycles: baseline architecture needs N clock for > > > N-point FFT > > > 4. Scalable to arbitrary large FFT size > > > 5. Multi-dimension extension: world's first 'intrinsic' > > > multi-dimensional FFT algorithm & architecture (not relay on 1-D FFTs) > > > : great for 2-D/3-D real-time medical imaging, SAR, etc. > > > > > > If you're interested in building a business together based on this > > > innovation, > > > please contact me with your resume. It'll be ideal if you have > > > contacts for potential customers. > > > > > > Any help on this matter from FPGA/DSP group members will be > > > appreciated. > > > > > > > > > Thanks. > > > > > > Seung P. Kim, Ph.D > > > Silicon Computing, Inc. > > > Mountain View, CA > > > > > >
> This will be your friend for long URLs. > http://tinyurl.com/
Please also include the full/long URL so google gets it. Shortcuts age and die after a while. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.