Problem with Virtex-4 IBIS model

I am setting up a signal integrity simulation of a Virtex-4 DDR2
memory interface with Agilent's ADS.
According to the readme file in the Virtex-4 IBIS distribution, on has
to add a "a 50-65 ohm transmission line with 10-200ps of delay" to
properly model package parasitics, so I have added a transmission line
between the driver output and the PCB load. The IBIS model, however,
already has a model for package parasitics (R_pkg, L_pkg, C_pkg) so I
am wondering how these will interact. From what I understand, this
transmission line models a trace in the "redistribution layer" inside
the BGA package, so ideally it should be embedded in the IBIS model
before R_pkg, L_pkg, C_pkg, not after, right?

Austin, do you have any recommendations?

Thanks

dudesinmexico wrote:
>
> According to the readme file in the Virtex-4 IBIS distribution, on has
> to add a "a 50-65 ohm transmission line with 10-200ps of delay" to
> properly model package parasitics, so I have added a transmission line
> between the driver output and the PCB load.
>
 What version/date are the IBIS files you're looking at?

 As of a couple years ago(?), Xilinx switched the V4 and V5
IBIS package modeling over to a coupled lumped model using a
separate .pkg file.

See chapter 4 of UG112 3v0, in particular page 70 onwards:
  http://www.xilinx.com/support/documentation/user_guides/ug112.pdf

 I don't think the older TLine modeling advice would be
applicable to these newer IBIS files using the package
coupling data; e.g. footnote 1 of UG112 table 4-3 reads:

  "The I/O data reflects the full FC interconnect chain-bump,
  the vias, traces, and external balls as depicted in Figure 4-3."

 Which I would interpret as saying that the RLC model in
the .pkg files incorporates the delays that were formerly
modeled with the TLine.

 (figures 4-6 and 4-8 are also quite handy)

 Based on past experiences with IBIS models and simulators,
I would advise first running some basic sanity checks to
verify that the simulator and vendor models are on the same
page with respect to package delays, on chip terminations, etc.

Brian

On Sep 12, 11:18=A0am, dudesinmexico <dudesinmex...@gmail.com> wrote:
> I am setting up a signal integrity simulation of a Virtex-4 DDR2
> memory interface with Agilent's ADS.
> According to the readme file in the Virtex-4 IBIS distribution, on has
> to add a "a 50-65 ohm transmission line with 10-200ps of delay" to
> properly model package parasitics, so I have added a transmission line
> between the driver output and the PCB load. The IBIS model, however,
> already has a model for package parasitics (R_pkg, L_pkg, C_pkg) so I
> am wondering how these will interact. From what I understand, this
> transmission line models a trace in the "redistribution layer" inside
> the BGA package, so ideally it should be embedded in the IBIS model
> before R_pkg, L_pkg, C_pkg, not after, right?
>
> Austin, do you have any recommendations?
>
> Thanks

I had similar questions for V5 and HyperLynx, so I opened a webcase.
Here is the reply I received:

--------------------------------
"However, I am not clear on what to do about the package parasitics,
R_pkg, L_pkg, and C_pkg.  AR#11754 says "there is a single set of RLC
numbers in the Virtex IBIS file that applies to all package types.
But virtex5.ibs actually contains a different set of numbers for each
package, all commented out.  The numbers that are uncommented are
labeled "Null Package", and they are all essentially zero.  The
download also included a file ff676_5vlx50_ibis.pkg, with a whole
bunch of RLC values in it."

-Correct, there is a set of RLC values in the ibis file labeled as
Null package.  This is just a generic set of RLC values.  If you are
not using the pkg file, you will need to uncomment the lines of the
RLC values for the package that you are using.  If you have an IBIS
simulator that uses the pkg file (such as IBIS writer), the pkg files
contain RLC information for every specific pin and overrides that RLC
information in the IBIS file.

"Question is, should I un-comment the values in virtex5.ibs for my
package (FF676)?  If yes, then do I still need to include the short
transmission line in LineSim, for the package signal trace?  Do I need
the other ".pkg" file for anything?"

-It depends on if you are using the pkg files.  If you are using the
pkg, don't worry about uncommenting the lines.  If you aren't using
the pkg file, uncomment the lines under your specific package.  The
pkg and IBIS file should include everything you need to properly
simulate your IOs.  It depends on what simulator you are using, but
the pkg file is a universal standard which most IBIS simulators will
use.
-------------------------------------------------------

So my understanding of this is that you either have the choice of
using the IBIS file (as is) along with the pkg file, or if you forget
about the pkg file, then modify the IBIS to use the R,L,C for your
specific package and include the trans lines in your circuit.  I chose
the latter, as I had no luck getting HyperLynx to use the pkg file.

Barry

On Sep 12, 7:32=A0pm, Brian Davis <brimda...@aol.com> wrote:
> dudesinmexico wrote:
>
> > According to the readme file in the Virtex-4 IBIS distribution, on has
> > to add a "a 50-65 ohm transmission line with 10-200ps of delay" to
> > properly model package parasitics, so I have added a transmission line
> > between the driver output and the PCB load.
>
> =A0What version/date are the IBIS files you're looking at?
>

The Virtex4 IBIS file is marked as IBIS version 3.2. This is the most
recent
IBIS file for V4 available for download from wwww.xilinx.com.

On Sep 15, 9:44=A0am, Barry <barry...@gmail.com> wrote:
> On Sep 12, 11:18=A0am, dudesinmexico <dudesinmex...@gmail.com> wrote:
>
> > I am setting up a signal integrity simulation of a Virtex-4 DDR2
> > memory interface with Agilent's ADS.
> > According to the readme file in the Virtex-4 IBIS distribution, on has
> > to add a "a 50-65 ohm transmission line with 10-200ps of delay" to
> > properly model package parasitics, so I have added a transmission line
> > between the driver output and the PCB load. The IBIS model, however,
> > already has a model for package parasitics (R_pkg, L_pkg, C_pkg) so I
> > am wondering how these will interact. From what I understand, this
> > transmission line models a trace in the "redistribution layer" inside
> > the BGA package, so ideally it should be embedded in the IBIS model
> > before R_pkg, L_pkg, C_pkg, not after, right?
>
> > Austin, do you have any recommendations?
>
> > Thanks
>
> I had similar questions for V5 and HyperLynx, so I opened a webcase.
> Here is the reply I received:
>
> --------------------------------
> "However, I am not clear on what to do about the package parasitics,
> R_pkg, L_pkg, and C_pkg. =A0AR#11754 says "there is a single set of RLC
> numbers in the Virtex IBIS file that applies to all package types.
> But virtex5.ibs actually contains a different set of numbers for each
> package, all commented out. =A0The numbers that are uncommented are
> labeled "Null Package", and they are all essentially zero. =A0The
> download also included a file ff676_5vlx50_ibis.pkg, with a whole
> bunch of RLC values in it."
>
> -Correct, there is a set of RLC values in the ibis file labeled as
> Null package. =A0This is just a generic set of RLC values. =A0If you are
> not using the pkg file, you will need to uncomment the lines of the
> RLC values for the package that you are using. =A0If you have an IBIS
> simulator that uses the pkg file (such as IBIS writer), the pkg files
> contain RLC information for every specific pin and overrides that RLC
> information in the IBIS file.
>
> "Question is, should I un-comment the values in virtex5.ibs for my
> package (FF676)? =A0If yes, then do I still need to include the short
> transmission line in LineSim, for the package signal trace? =A0Do I need
> the other ".pkg" file for anything?"
>
> -It depends on if you are using the pkg files. =A0If you are using the
> pkg, don't worry about uncommenting the lines. =A0If you aren't using
> the pkg file, uncomment the lines under your specific package. =A0The
> pkg and IBIS file should include everything you need to properly
> simulate your IOs. =A0It depends on what simulator you are using, but
> the pkg file is a universal standard which most IBIS simulators will
> use.
> -------------------------------------------------------
>
> So my understanding of this is that you either have the choice of
> using the IBIS file (as is) along with the pkg file, or if you forget
> about the pkg file, then modify the IBIS to use the R,L,C for your
> specific package and include the trans lines in your circuit. =A0I chose
> the latter, as I had no luck getting HyperLynx to use the pkg file.
>
> Barry

Brian and Barry, thanks for sharing your experience.

It is still not clear whether one has to add the transmission line
model.
The readme.txt file in the V4 IBIS distribution says to do so, while
at
page 73 of UG112, Note 1. of Tb. 4-3 reads: "The I/O data reflects the
full FC interconnect chain-bump, the vias, and external balls as
depicted in Fig. 4-3."

This is all very confusing...

On Sep 15, 12:44 pm, Barry <barry...@gmail.com> wrote:
>
> So my understanding of this is that you either have the choice of
> using the IBIS file (as is) along with the pkg file, or if you forget
> about the pkg file, then modify the IBIS to use the R,L,C for your
> specific package and include the trans lines in your circuit.
>

 But Xilinx's response to your question makes no mention of including
those Tlines in the simulation model:

> -It depends on if you are using the pkg files.  If you are using the
> pkg, don't worry about uncommenting the lines.  If you aren't using
> the pkg file, uncomment the lines under your specific package.  The
> pkg and IBIS file should include everything you need to properly
> simulate your IOs.  It depends on what simulator you are using, but
> the pkg file is a universal standard which most IBIS simulators will
> use.

 My understanding of this is as follows:

  - if you use the IBIS header values by uncommenting the header
    for a specific package, you get a generic uncoupled lumped model
    with min/typ/max values representative of that package type

  - if you use the .pkg file, you get a coupled lumped model that
    models each pin of the package distinctly

 In neither case should you use the Tlines with these newer IBIS
files,
as that delay is now included in the lumped package model.

( I haven't any first hand experience with Hyperlynx in over five
years,
so take the above advice with an appropriately sized lump of salt. )

 I'm working on a more detailed reply to "dudesinmexico" with some
notes about the IBIS modeling changes, but I don't know if I'll have
time to post it tonight.

Brian

dudesinmex...@yahoo.com wrote:
>
> It is still not clear whether one has to add the
> transmission line model.
>
> The readme.txt file in the V4 IBIS distribution says to do so,
> while at page 73 of UG112, Note 1. of Tb. 4-3 reads: "The I/O
> data reflects the full FC interconnect chain-bump, the vias,
> and external balls as depicted in Fig. 4-3."
>

 I'd go with UG112 on this one.

 I believe the statement in the V4 readme file is just a
case of "copy the old readme" from the earlier releases
of the V4 IBIS models, as the V5 models, using the exact
same type of lumped model, do NOT have that note about
needing to add the Tlines.

 Nor would it be unusual for an Answer Record (11754)
to be out of date.

----------------------

 I'd also take a look at this video ( which I haven't
actually watched yet ):

http://signal-integrity-tips.com/2008/workflow-with-ibis-models/

 Squinting at the initial screen dumps, it doesn't look
like they added the extra Tline ( the next blob over from
the Xilinx IBIS buffer looks like a via model ).

 I'd ask your ADS FAE if there's a copy of the associated
ADS files for that ADS Xilinx/Micron IBIS simulation, and
see which version of the Xilinx IBIS files the ADS modeling
used, and whether the ADS gurus used the extra Tline.

>
> The Virtex4 IBIS file is marked as IBIS version 3.2.
>
Note, the revision of importance here is not the IBIS file
format version, but the one labeled [File Rev], which AFAIK
is currently 2.5.1 for Virtex4.

 Comparing the older IBIS files to this newer version:

 - In the earlier (2.2) IBIS files, using the Tline,
   there is one and only one set of package parasitics,
   with teeny values for L_pkg and C_pkg. ( less than
   one nH and one pF each ).

 - In the newer (2.5.1) IBIS files, no Tline required,
   there is a heftier value, for each type of package,
   of a few or more nHs and pFs each.


 Which I believe supports my interpretation that the delay
formerly modeled by the Tline now shows up in the lumped
LCR package model, as also explained in UG112.


Brian

Much earlier, I wrote:
>
>  My understanding of this is as follows:
>
>   - if you use the IBISheader values by uncommenting the header
>     for a specific package, you get a generic uncoupled lumped model
>     with min/typ/max values representative of that package type
>
>   - if you use the .pkg file, you get a coupled lumped model that
>     models each pin of the package distinctly
>
>  In neither case should you use the Tlines with these newer IBIS
> files, as that delay is now included in the lumped package model.
>

 I recently stumbled across a related Answer Record, 21632, whilst
seaching for Something Completely Different:

http://www.xilinx.com/support/answers/21632.htm

" AR #21632 - How do I integrate per pin parasitic package data
" (in the .pkg file) provided in the IBIS archive into the IBIS file?

Brian