rs232 uart: testbench vs real world, and the missing first letter.

On Feb 4, 1:32=A0am, Bob Smith <use...@linuxtoys.org> wrote:
> Hi,
>
> I would like to use a Spartan 3 100K FPGA to implement 16
> serial ports. =A0The ports will be fairly simple: 1200 to
> 115200 baud, Tx, Rx, and two flow control lines per port.
>
> I already have a working serial port and could make sixteen
> instances of it. =A0This would chew up a lot of the FPGA.
>
> Is there a better way to build sixteen serial ports?
>
> Would it make sense to build one serial port and try to
> time division multiplex it to the sixteen sets of inputs,
> perhaps keeping all state information in RAM? =A0Is this a
> feasible or reasonable approach?

When you say 16 serial ports will chew up a lot of the FPGA, have you
measured the size of a simple UART?  If you need a complex UART with
FIFOs and handshake controls, I doubt that you will be able to save
much by somehow combining them.  But if you can use a simple UART with
just data in each direction and just a holding register, I suspect
even 16 of these will not be a big design.  If it is, you can build a
state machine that uses the LUTs as distributed RAM to emulate 16
registers and end up with a pretty optimized design.

I just think this will be more work than it is worth.  A simple UART
should be on the order of 50 LUTs (I'm estimating here) so even x16
that would only be 800 of almost 2000 LUTs... maybe that *is* a lot.
A sized optimized N duplicated UART might be an interesting design.

Rick

Bob Smith wrote:
> Would it make sense to build one serial port and try to
> time division multiplex it to the sixteen sets of inputs,
> perhaps keeping all state information in RAM?  Is this a
> feasible or reasonable approach?

Thanks Glen, JG, Rick.

I may try this with something a little easier like a PWM
controller.

thanks
Bob Smith