I'm trying to run through simulation of the PIO example given with Xilinx PCIe endpoint block plus. However, when I run modelsim with the .do file given in the example, I get: vmap work {C:/Documents and Settings/PoojanW/My Documents/PCIeEPBP/ pciex4/simulation/functional/work} # Copying c:\modeltech_pe_6.5\win32pe/../modelsim.ini to modelsim.ini # Modifying modelsim.ini # ** Warning: Copied c:\modeltech_pe_6.5\win32pe/../modelsim.ini to modelsim.ini. # Updated modelsim.ini. vlib work # ** Warning: (vlib-34) Library already exists at "work". vmap work # Reading modelsim.ini # "work" maps to directory C:/Documents and Settings/PoojanW/My Documents/PCIeEPBP/pciex4/simulation/functional/work. vcom -work work -f board_rtl.f # Model Technology ModelSim PE vcom 6.5 Compiler 2009.01 Jan 22 2009 # -- Loading package standard # ** Error: ../../example_design/xilinx_pci_exp_ep.v(1): near "/": syntax error # ** Error: ../../../pciex4.v(1): VHDL Compiler exiting # c:/modeltech_pe_6.5/win32pe/vcom failed. (For illustration, I executed the .do file manually line by line). I don't know much about ModelSim (thus the post), but it seems like it thinks ../../example_design/xilinx_pci_exp_ep.v is a VHDL file (rather than Verilog). How do I fix this misunderstanding?
Problem with ModelSim and Xilinx PCIe endpoint block plus simulation
Started by ●February 17, 2009
Reply by ●February 17, 20092009-02-17
Poojan Wagh wrote:> I'm trying to run through simulation of the PIO example given with > Xilinx PCIe endpoint block plus. However, when I run modelsim with > the .do file given in the example, I get: > > vmap work {C:/Documents and Settings/PoojanW/My Documents/PCIeEPBP/ > pciex4/simulation/functional/work} > # Copying c:\modeltech_pe_6.5\win32pe/../modelsim.ini to modelsim.ini > # Modifying modelsim.ini > # ** Warning: Copied c:\modeltech_pe_6.5\win32pe/../modelsim.ini to > modelsim.ini. > # Updated modelsim.ini. > vlib work > # ** Warning: (vlib-34) Library already exists at "work". > vmap work > # Reading modelsim.ini > # "work" maps to directory C:/Documents and Settings/PoojanW/My > Documents/PCIeEPBP/pciex4/simulation/functional/work. > vcom -work work -f board_rtl.f > # Model Technology ModelSim PE vcom 6.5 Compiler 2009.01 Jan 22 2009 > # -- Loading package standard > # ** Error: ../../example_design/xilinx_pci_exp_ep.v(1): near "/": > syntax error > # ** Error: ../../../pciex4.v(1): VHDL Compiler exiting > # c:/modeltech_pe_6.5/win32pe/vcom failed. > > (For illustration, I executed the .do file manually line by line). > > I don't know much about ModelSim (thus the post), but it seems like it > thinks ../../example_design/xilinx_pci_exp_ep.v is a VHDL file > (rather than Verilog). How do I fix this misunderstanding?You could try right-clicking on the project, selecting Properties, and setting the preferred language to Verilog? I don't know if this will help, but it's worth a try, Alan -- Alan Fitch http://www.doulos.com
Reply by ●February 18, 20092009-02-18
On Tue, 17 Feb 2009 15:37:53 -0800 (PST), Poojan Wagh <poojanwagh@gmail.com> wrote:>I'm trying to run through simulation of the PIO example given with >Xilinx PCIe endpoint block plus. However, when I run modelsim with >the .do file given in the example, I get: >>vcom -work work -f board_rtl.f ># Model Technology ModelSim PE vcom 6.5 Compiler 2009.01 Jan 22 2009 ># -- Loading package standard ># ** Error: ../../example_design/xilinx_pci_exp_ep.v(1): near "/": >syntax error>(For illustration, I executed the .do file manually line by line). > >I don't know much about ModelSim (thus the post), but it seems like it >thinks ../../example_design/xilinx_pci_exp_ep.v is a VHDL file >(rather than Verilog). How do I fix this misunderstanding?The problem is apparently in the example script. vcom is the VHDL compiler, which IMO can legitimately assume its input is VHDL... I think you need to edit the script (or find a more suitable one) to use the Verilog compiler. I think it's called vlog, but I've never used it. - Brian