Virtex-5 DDRII SRAM Calibration Issues

Hi guys,

I'm trying to use a MIG v2.3 generated DDRII SRAM controller to verify our
hardware for a 36 Mb, x18, Burst length 4, GSI SRAM chip. We're using a
Virtex-5 LX110T chip with a 1738 package size.

The design passes stage 1 calibration but hangs during stage 2
calibration. The same behaviour is exhibited when running the controller at
250 MHz or 200 MHz. Both the controller and the SRAM chip in question have
been verified in simulation (memory test and all calibration stages pass).
I had heard that the Xilinx tap controller does not have a large enough
window to allow certain devices to operate with worst case datasheet
timing...

Any thoughts as to what might be occurring?

cheers,
Colin