Xilinx Mig bus functional model?

I'm starting to play with the Xilinx Mig for a DDR2 design. I have the
basic
logic generated by Mig simulating and the DDR2 model seems to be
twitching
happily.  Of course, it takes a while to simulate through the DDR2
setup
and calibration.

Does anyone have a bus function model of the user interface to the Mig
DDR2 controller,
ie, the app_* interface?

I don't need/want to simulate the DDR2 interface for a lot of my tests
and
I'd like to have a simple memory model using the app* interface for a
lot
of my testing to speed up the development.

Thanks in advance.

John Providenza