Spartan3E Starter Kit MISO and Flash pin shared

On May 6, 12:42=A0am, "mstanisz" <matt.staniszew...@gmail.com> wrote:
> I've searched a little more and found that if I can somehow merge Ben
> Cohen's 0 ohm device
> (http://groups.google.com/group/comp.lang.vhdl/msg/7d14832588a0cabb) with
> a
> bi-directional MUX
> (http://www.tek-tips.com/viewthread.cfm?qid=3D1188582&page=3D7), then I m=
ight
> be able to create the VHDL module I would need. =A0The bus splitting
> doesn't
> need a module, since in VHDL I'll just manipulate bit0 of the inputted
> flash data bus and pass the other 7 bits through. =A0Would this work?
> Thanks.
>
> Matt
>
>
>
>
>
> >The MISO and data<0> signals are bidirectional (IO). =A0Can you make a
> >mux/switcher and bus splitter for bidirectional signals?
>
> >Matt
>
> >>"mstanisz" <matt.staniszew...@gmail.com> wrote in message
> >>news:19mdndgAN665R2LUnZ2dnUVZ_qadnZ2d@giganews.com...
> >>> Okay, I went ahead and removed the duplicate NETs in the UCF and made
> >them
> >>> internal. =A0I'm trying to figure out how to MUX between the two
> signals
> >>> using a core in EDK. =A0It does seem like it should be fairly simple,
> but
>
> >>> I'm
> >>> not sure how to go about it with IP cores. =A0Thanks.
>
> >>Minimally, define a module with OUT pins for the two now disconnected
> >nets,
> >>additional pins for selection, and an IN pin for the external net. Add
> >the
> >>external net to the UCF. This is exactly as you would do for any old
> >simple
> >>design. There might already be an example or usable hdl in the samples
> >files
> >>for that board.
>
> >>My normal workflow wraps the EDK project in an ISE project. Instantiate
> >the
> >>switcher/mux in the top most module, at the same level you instantiate
> >the
> >>EDK system. Swap and mix the pins as you need. Take a look at (for a
> >project
> >>named system.xmp) hdl/system_stub.vhd for an example of instantiating
> the
>
> >>EDK system.
>
> >>I think it would be a bad idea to tear into the pcore hdl or wrappers
> to
> >do
> >>this.- Hide quoted text -
>
> - Show quoted text -

you need

own small EDK IP, that


connects to xx_I xx_T xx_O busses (from the parallel flash core,
you need make this bus internal) and to your signal. you need to mux
using control signal, the new IP exposes the new bus to be exported

takes about 30 minutes to make


Antti

"mstanisz" <matt.staniszewski@gmail.com> wrote in message 
news:0f2dnf-i_aMyL53XnZ2dnUVZ_hqdnZ2d@giganews.com...
> I've searched a little more and found that if I can somehow merge Ben
> Cohen's 0 ohm device
> (http://groups.google.com/group/comp.lang.vhdl/msg/7d14832588a0cabb) with
> a
> bi-directional MUX
> (http://www.tek-tips.com/viewthread.cfm?qid=1188582&page=7), then I might
> be able to create the VHDL module I would need.  The bus splitting
> doesn't
> need a module, since in VHDL I'll just manipulate bit0 of the inputted
> flash data bus and pass the other 7 bits through.  Would this work?
> Thanks.
>
> Matt

You'll still need logic to figure out which personality is active.

No one here is likely to write it for you, as this is a seminal moment in 
your learning. There's quite a bit involved, but they're all small and 
nothing by itself is overwhelming.

Step away from the immediate problem, and take it a step at a time. Start 
with a basic, empty ISE project, and wire one user I/O pin for dual 
functions as you have in the actual problem. Setup up a testbench and play 
with it in simulation. The immediate problem is strictly behavioral, so it 
should simulate well before moving on.

What are the roles of CE#, WE#, and SPI CS? Can you safely arbitrate 
conflicts? What effect does the additional logic have on signal timing? What 
are those requirements, and how do you specify them in the design?

Once it's working, how will you integrate it into EDK? Antii's suggestion of 
a pcore you can reuse is a good one. Another way is to wrap the xmp system 
in an overall design, and instantiate it there.



>
>>The MISO and data<0> signals are bidirectional (IO).  Can you make a
>>mux/switcher and bus splitter for bidirectional signals?
>>
>>Matt
>>
>>>"mstanisz" <matt.staniszewski@gmail.com> wrote in message
>>>news:19mdndgAN665R2LUnZ2dnUVZ_qadnZ2d@giganews.com...
>>>> Okay, I went ahead and removed the duplicate NETs in the UCF and made
>>them
>>>> internal.  I'm trying to figure out how to MUX between the two
> signals
>>>> using a core in EDK.  It does seem like it should be fairly simple,
> but
>>
>>>> I'm
>>>> not sure how to go about it with IP cores.  Thanks.
>>>
>>>Minimally, define a module with OUT pins for the two now disconnected
>>nets,
>>>additional pins for selection, and an IN pin for the external net. Add
>>the
>>>external net to the UCF. This is exactly as you would do for any old
>>simple
>>>design. There might already be an example or usable hdl in the samples
>>files
>>>for that board.
>>>
>>>My normal workflow wraps the EDK project in an ISE project. Instantiate
>>the
>>>switcher/mux in the top most module, at the same level you instantiate
>>the
>>>EDK system. Swap and mix the pins as you need. Take a look at (for a
>>project
>>>named system.xmp) hdl/system_stub.vhd for an example of instantiating
> the
>>
>>>EDK system.
>>>
>>>I think it would be a bad idea to tear into the pcore hdl or wrappers
> to
>>do
>>>this.
>>>
>>>
>>