Doubt about a Microblaze Based Multiprocessor SoC

On Jun 11, 1:45=A0am, "naim32" <engineer_n...@yahoo.com> wrote:
> >> Hi,
>
> >> I am new to this site but i found the topic very helpful for me. I
> just
> >> need to know if the DDR memory is the only memory that can store MPSoC
> >> systems (up to 8 Microblaze systems) on the ML403 board. Can we use
> the
> >> SRAM too? And how much would it hold (up to how many microblaze
> >> processors)? and in case I am using the FPGA's BRAMs as cache
> memories,
> >> would that affect how many microblaze that could be added?
>
> >> Thanks a lot,
> >> N
>
> >No external memories are required by a MB since its elf and stack/heap
> >can be stored in local BRAM. On large fpgas you can probably squeeze
> >in at least a dozen MB. If the elf or stack/heap is so large that it
> >doesn't fit in BRAM, then you can also use external DDR2 or SRAM or
> >Flash. Using BRAM for other purposes simply reduces the amount
> >available for MB(s).
>
> >The DDR2 uses the Xilinx multiport memory controller (MPMC described
> >in DS643) with max 8 ports per bank, while the SRAM (or Flash) uses
> >the Xilinx multi-channel external memory controller (XPS MCH EMC
> >described in DS575) with max 4 ports. On the Xilinx MLxxx boards there
> >is only 1 bank of DDR2, SRAM or Flash, while other boards may have
> >multiple banks.
>
> >For higher throughput and higher energy efficiency, it makes sense to
> >move functionality from sw targets to hw targets.
> >/Per
>
> Thanks for the quick feedback, and I am sorry but I am quite new to the
> MPSoC domain on the Xilinx boards.
>
> The thing is that I have to use 12 Microblaze processors on my FPGA (ML40=
3
> board). The code segment of all of them doesn't fit on the local BRAMs in
> the FPGA and that is why I am in need to use external memories to store
> this segment. Also, I wish to use the BRAMs as cache memories for these M=
Bs
> (I and D cache). My main question is: can I fit 12 Microblaze processors =
on
> external memory (on DDR or SRAM)? Let us say I have one MPMC controller
> with 8 ports, can I add another controller with different start and end
> addresses than the previous and then I will have 16 ports?
>
> Thanks in advance
> N

You can't chain MPMCs -- the SDRAM port is not compatible with the
user port. You can potentially use 8x MB using a MPMC and 4x MB using
MCHEMC, but I've never tried that. I'm also not sure that 12 MB fit on
a ML403 (which is rather small).

Why 12 MB? Moving functionality from sw to hw is normally recommended.

>
>You can't chain MPMCs -- the SDRAM port is not compatible with the
>user port. You can potentially use 8x MB using a MPMC and 4x MB using
>MCHEMC, but I've never tried that. I'm also not sure that 12 MB fit on
>a ML403 (which is rather small).
>
>Why 12 MB? Moving functionality from sw to hw is normally recommended.
>

I have to migrate a system into my board and compare them. If 12 can not
fit, its okay. I have one more question regarding the DDR, I can add up to
8x MBs on the DDR each including I and D cache? I mean, if I enabled the I
and D cache for my MBs, still I can fit 8 on the DDR?

Thanks
N

On Jun 11, 12:28=A0pm, "naim32" <engineer_n...@yahoo.com> wrote:
> >You can't chain MPMCs -- the SDRAM port is not compatible with the
> >user port. You can potentially use 8x MB using a MPMC and 4x MB using
> >MCHEMC, but I've never tried that. I'm also not sure that 12 MB fit on
> >a ML403 (which is rather small).
>
> >Why 12 MB? Moving functionality from sw to hw is normally recommended.
>
> I have to migrate a system into my board and compare them. If 12 can not
> fit, its okay. I have one more question regarding the DDR, I can add up t=
o
> 8x MBs on the DDR each including I and D cache? I mean, if I enabled the =
I
> and D cache for my MBs, still I can fit 8 on the DDR?
>
> Thanks
> N

I've run 8x MB (without caches), but don't remember if it was a ML4xx
or ML5xx. Allocating (unused) BRAM to caches should be fine.

>
>I've run 8x MB (without caches), but don't remember if it was a ML4xx
>or ML5xx. Allocating (unused) BRAM to caches should be fine.
>

Thank you for the feedback, I will try the system tomorrow and will post
the results soon... Again Thank you