DDS-Based PLL

"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:eHVfc.145675$gA5.1776343@attbi_s03...
> The applications I was thinking of mostly is sampling clocks for ADCs or
> DACs, so having low jitter is important and in that case using the MSB of
a
> DDS wouldn't suffice.  I had one application in which I had to generate a
> DAC clock that wasn't really large but was a really strange multiple of an
> input clock (the ratio was close to 80000/78000, irreducable) and PLLs
> couldn't handle that ratio and even if they could the comparison frequency
> would be really low and the loop filter cutoff would have had to be really
> small.
>
> I like the offset idea.  Of course that means you need an accurate
> high-frequency source with which to mix; I guess that would be generated
> with a PLL.
> -Kevin


The jitter associated with *most* digital-based clocking techniques is tough
to deal with for ADC and DAC systems without the PLL and VCO.  What *can* be
done to get the irreducably low frequency to not cripple your system is to
not go so low....  Fractional-N synthesizers can give superb spectral
results with non-integer divides.  In some cases, these Fractional-N devices
which "dither" the divider before the phase comparator can produce close-in
harmonics that aren't reasonable to filter.  With arbitrary numerator and
denominator values (producing an odd modulus in the accumulator) these
close-in sidebands can be pushed out to well beyond the PLL's loop filter
cutoff.  With sigma-delta techniques in some of the commercially available
Fractional-N synthesizers, some problem sidebands can be squashed.  Neat
stuff, all of it.

- John_H

Peter Alfke wrote:
> Fine frequency resolution with reasonably low jitter.
> 
> I just finished and tested an FPGA design using a 30-bit DDS phase
> accumulator that is conservatively clocked at 80 MHz and, with the help of a
> DCM in Frequency Synthesis mode and a binary divider chain, generates any
> frequency from 1 Hz to 80 MHz with 1 Hz granularity.
> The output period jitter is <300 picoseconds peak-to-peak.
> There is a roadmap to increase the output frequency to max 5 GHz at
> substantially reduced jitter.

  Seems there's a lot packed into a few sentences here - when/where can 
we see more info  ?
-jg