Reading from ADC and writing to DAC at same time

Hello--

I'm setting up a circuit where I need to write data to a DAC at the same 
time as read data from 8 ADCs.

I need to shift a data word out to the DAC to set an output voltage.  At 
the same time, I need to read data from each ADC.

The DAC and the ADCs all communicate over SPI.  The maximum sampling 
rate of each 18-bit ADC is 400 kHz.  The maximum update rate of each 
16-bit DAC is 400 kHz, the same as the sampling rate as the ADC.

Sampling from each ADC is triggered using a /TRIGGER pin.  I believe 
that it is possible to daisy-chain the ADCs.

Perhaps the best way to do this is to use a FPGA.  I suppose that I 
would set up a separate SPI bus for each ADC and DAC, and separate /CS 
lines. All of the ADCs and DACs would not be on the same SPI bus.

As the data is harvested from each ADC, I could shift the data into 
SDRAM. Once the measurement sequence is complete, the main system micro- 
controller could read the data from the FPGA SDRAM by using the FPGA as 
an SPI slave.

Is this a good way to proceed? My first initiative is to perhaps use a 
Cyclone III FPGA with 3.3V SDRAM logic, although I think that there are 
probably other FPGAs that could work just as well.

Are there any free/gratis megafunction solutions for SPI and 
communication with SDRAM logic?

What should I choose to be the clock speed on the FPGA, based on the 
maximum SPI bus rates?  The DAC has a maximum SPI clock of 30 MHz, and 
the max clock speed of the ADC is at least 50 MHz.

On Aug 26, 7:54=A0am, Nicholas Kinar <n.ki...@usask.ca> wrote:
> Hello--
>
> I'm setting up a circuit where I need to write data to a DAC at the same
> time as read data from 8 ADCs.
>
> I need to shift a data word out to the DAC to set an output voltage. =A0A=
t
> the same time, I need to read data from each ADC.
>
> The DAC and the ADCs all communicate over SPI. =A0The maximum sampling
> rate of each 18-bit ADC is 400 kHz. =A0The maximum update rate of each
> 16-bit DAC is 400 kHz, the same as the sampling rate as the ADC.
>
> Sampling from each ADC is triggered using a /TRIGGER pin. =A0I believe
> that it is possible to daisy-chain the ADCs.
>
> Perhaps the best way to do this is to use a FPGA. =A0I suppose that I
> would set up a separate SPI bus for each ADC and DAC, and separate /CS
> lines. All of the ADCs and DACs would not be on the same SPI bus.
>
> As the data is harvested from each ADC, I could shift the data into
> SDRAM. Once the measurement sequence is complete, the main system micro-
> controller could read the data from the FPGA SDRAM by using the FPGA as
> an SPI slave.
>
> Is this a good way to proceed? My first initiative is to perhaps use a
> Cyclone III FPGA with 3.3V SDRAM logic, although I think that there are
> probably other FPGAs that could work just as well.
>
> Are there any free/gratis megafunction solutions for SPI and
> communication with SDRAM logic?
>
> What should I choose to be the clock speed on the FPGA, based on the
> maximum SPI bus rates? =A0The DAC has a maximum SPI clock of 30 MHz, and
> the max clock speed of the ADC is at least 50 MHz.

why do you think you need SDRAM?

what you need is just a statemachine-sequencer-special purpose SPI
engine
that places the results into dual port block ram (available in any
FPGA)

and as you requests are not standard you need to write the code from
scratch

Antti

Antti.Lukats@googlemail.com wrote:

> why do you think you need SDRAM?
> 
> what you need is just a statemachine-sequencer-special purpose SPI
> engine
> that places the results into dual port block ram (available in any
> FPGA)

This depends on how long he wants to sample. If he needs some kilobytes,
block RAM would be ok. If it is below a megabyte, I would suggest SRAM,
because it is much easier to write your own VHDL code for it. And I would
use a ready made module, like this one, at least for the prototyping phase,
if it is going to be a product:

http://shop.trenz-electronic.de/catalog/product_info.php?cPath=1_48&products_id=81

More expensive, but with more pins and SDRAM instead of SRAM:

http://www.enterpoint.co.uk/moelbryn/darnaw1.html

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Thanks for your response, Antti.

> 
> why do you think you need SDRAM?
> 

Perhaps to store large amounts of data from all of the 6 ADCSs?

> what you need is just a statemachine-sequencer-special purpose SPI
> engine
> that places the results into dual port block ram (available in any
> FPGA)
> 

That is an interesting idea. But how much RAM do I generally have available?


> and as you requests are not standard you need to write the code from
> scratch

Would SPI be a challenge to implement in the way that I have described?

Frank Buss wrote:
> Antti.Lukats@googlemail.com wrote:
> 
>> why do you think you need SDRAM?
>>
>> what you need is just a statemachine-sequencer-special purpose SPI
>> engine
>> that places the results into dual port block ram (available in any
>> FPGA)
> 
> This depends on how long he wants to sample. If he needs some kilobytes,
> block RAM would be ok. If it is below a megabyte, I would suggest SRAM,
> because it is much easier to write your own VHDL code for it. And I would
> use a ready made module, like this one, at least for the prototyping phase,
> if it is going to be a product:
> 
> http://shop.trenz-electronic.de/catalog/product_info.php?cPath=1_48&products_id=81
> 
> More expensive, but with more pins and SDRAM instead of SRAM:
> 
> http://www.enterpoint.co.uk/moelbryn/darnaw1.html
> 


Sounds good, Frank.  Thank you for your response. Do you think that most 
of this stuff could be easily done in Verilog as well?

SRAM sounds nice, but isn't there some sort of reference 
implementation/plugin/megafunction for accessing this type of memory?

On Aug 26, 8:40=A0am, Nicholas Kinar <n.ki...@usask.ca> wrote:
> Thanks for your response, Antti.
>
>
>
> > why do you think you need SDRAM?
>
> Perhaps to store large amounts of data from all of the 6 ADCSs?
>
> > what you need is just a statemachine-sequencer-special purpose SPI
> > engine
> > that places the results into dual port block ram (available in any
> > FPGA)
>
> That is an interesting idea. But how much RAM do I generally have availab=
le?
>
> > and as you requests are not standard you need to write the code from
> > scratch
>
> Would SPI be a challenge to implement in the way that I have described?


SPI =3D VERY simple
SRAM =3D SIMPLE

the amount of BRAM depends on the FPGA, i think smallest cyclone-3 has
66 KByte
(smallest spartan3a has only 6KByte)

for SRAM, well there are of course IP cores that use SRAM, but those
are most
like soft-processor bus attachments, so not necessarily much help for
you

but SRAM access is really very simple, not compared to the pain that
it is needed for SDRAM

GOP200 module is real nice small cute thing, I have one on my desk too
trenz is also very soon having S3ADSP low cost modules with SDRAM
/ but S3ADSP1800 has already 126KB of BRAM

Antti

Nicholas Kinar <n.kinar@usask.ca> wrote:
 
< I'm setting up a circuit where I need to write data to a DAC at the same 
< time as read data from 8 ADCs.
 
< I need to shift a data word out to the DAC to set an output voltage.  At 
< the same time, I need to read data from each ADC.
 
< The DAC and the ADCs all communicate over SPI.  The maximum sampling 
< rate of each 18-bit ADC is 400 kHz.  The maximum update rate of each 
< 16-bit DAC is 400 kHz, the same as the sampling rate as the ADC.

How fast is SPI?
 
< Sampling from each ADC is triggered using a /TRIGGER pin.  I believe 
< that it is possible to daisy-chain the ADCs.

Maybe not if the bus isn't that fast.
 
< Perhaps the best way to do this is to use a FPGA.  I suppose that I 
< would set up a separate SPI bus for each ADC and DAC, and separate /CS 
< lines. All of the ADCs and DACs would not be on the same SPI bus.

Separate SPI bus would allow each to run at full speed.
 
< As the data is harvested from each ADC, I could shift the data into 
< SDRAM. Once the measurement sequence is complete, the main system micro- 
< controller could read the data from the FPGA SDRAM by using the FPGA as 
< an SPI slave.

Why store it in SDRAM?  Process it and send it out immediately.

Well, 400kHz isn't so fast, but you could just build a state
machine in the FPGA.  Otherwise you might just as well use
any old processor.
 
-- glen

> 
> SPI = VERY simple
> SRAM = SIMPLE
> 

Yes, I agree that SPI and SRAM are simple.


> 
> GOP200 module is real nice small cute thing, I have one on my desk too
> trenz is also very soon having S3ADSP low cost modules with SDRAM
> / but S3ADSP1800 has already 126KB of BRAM
> 
> Antti


I'll check it out, thanks Antti.

Thanks, Glen.

> How fast is SPI?
>  

Maximum 30MHz, I believe.

> 
> Why store it in SDRAM?  Process it and send it out immediately.
> 

Perhaps what this would guarantee is "real-time," especially when 
working with Linux-based microcontrollers.


> Well, 400kHz isn't so fast, but you could just build a state
> machine in the FPGA.  Otherwise you might just as well use
> any old processor.
>  

Sure, even if the processor is running Linux, "almost real-time" is 
sometimes less complex than real-time.

Perhaps all of the ADCs and the DAC could be wired to the same bus?

On 26 Aug., 06:54, Nicholas Kinar <n.ki...@usask.ca> wrote:
> Hello--
>
> I'm setting up a circuit where I need to write data to a DAC at the same
> time as read data from 8 ADCs.
>
> I need to shift a data word out to the DAC to set an output voltage. =A0A=
t
> the same time, I need to read data from each ADC.
>
> The DAC and the ADCs all communicate over SPI. =A0The maximum sampling
> rate of each 18-bit ADC is 400 kHz. =A0The maximum update rate of each
> 16-bit DAC is 400 kHz, the same as the sampling rate as the ADC.
>
> Sampling from each ADC is triggered using a /TRIGGER pin. =A0I believe
> that it is possible to daisy-chain the ADCs.
>
> Perhaps the best way to do this is to use a FPGA. =A0I suppose that I
> would set up a separate SPI bus for each ADC and DAC, and separate /CS
> lines. All of the ADCs and DACs would not be on the same SPI bus.
>
> As the data is harvested from each ADC, I could shift the data into
> SDRAM. Once the measurement sequence is complete, the main system micro-
> controller could read the data from the FPGA SDRAM by using the FPGA as
> an SPI slave.
>
> Is this a good way to proceed? My first initiative is to perhaps use a
> Cyclone III FPGA with 3.3V SDRAM logic, although I think that there are
> probably other FPGAs that could work just as well.
>
> Are there any free/gratis megafunction solutions for SPI and
> communication with SDRAM logic?
>
> What should I choose to be the clock speed on the FPGA, based on the
> maximum SPI bus rates? =A0The DAC has a maximum SPI clock of 30 MHz, and
> the max clock speed of the ADC is at least 50 MHz.

shouldn't need to read and write at the same time if the ADCs have a
trigger pin,

write the DAC value, hit the trigger to all ADCs, with a fast spi clk
there's then
plenty of time to read the ADCs one at a time before the next cycle

-Lasse