On Oct 15, 9:35=A0am, "dc207" <jaap....@planet.nl> wrote:> >... but do the data errors disappear? > > Yes, the data errors disappear like "snow in the sun" with the external > (on-board) termination resistor.... >What is the time-constant of the RC effect, and final peak/DC amplitudes ? Can you reproduce that same waveform and ~error rates with a deliberately incorrect termination ?. With multiple channels, you could run some external, some internal term, and a couple of 'experimental' ones that you tune to degrade the error rate to around the failing ones. That gives a feel for just how far off it needs to be to spawn the errors. -jg
FPGA on-die LVDS termination issues
Started by ●October 13, 2009
Reply by ●October 14, 20092009-10-14
Reply by ●October 17, 20092009-10-17
Earlier, I wrote:> > A bug later on in the flow ( e.g. Bitgen ) could have this effect >on the hardware yet still show the terminations in the FPGA editor. >Thinking about this further, it occurred to me that what you are most likely chasing is not an obscure bug in Bitgen that broke the differential terminators, but rather a simple mistake in your IBIS simulation. The HyperLynx/Xilinx DIFF_TERM problems that I linked to earlier are fairly old; if you are doing your simulation of an LVDS_25_DT input with a version of HyperLynx >=3D v7.5, it is ALREADY MODELING the input termination of the V4. If you then added a HyperLynx "quick terminator" thinking that it was NOT modeling the on-die termination, your simulation now has an EXTRA termination where your actual board does not. So by adding one to your board, your board better matches the sim... --------------------- As I pointed in that 2006 ADS572x thread, linked to in my earlier post, the output drivers of these particular DACs are high impedance current sources, without any back termination, capable of sub-200 ps edges. It is extremely hazardous to the health of your data to connect them to a Xilinx FPGA having 10 pf Cin (single ended) without providing some sort of back termination. TI's ADS527x datasheet has a paragraph stating exactly that: http://focus.ti.com/lit/ds/symlink/ads5273.pdf [ ads5273.pdf, Rev D, Jan. 2009, page 23 ] " " The single-ended output impedance of the LVDS drivers is very " high because they are current-source driven. If there are " excessive reflections from the receiver, it might be necessary " to place a 100=E2=84=A6 termination resistor across the outputs of the " LVDS drivers to minimize the effect of reflections " --------------------- Many of TI's newer LVDS A/D's now include a selectable back termination on the LVDS outputs. The ADS6423 datasheet has a nice set of plots showing some data waveforms with/without the back termination switched in. ads6423.pdf, Rev A, June 2007, page 56, figures 79 & 80 http://focus.ti.com/lit/ds/symlink/ads6423.pdf Looking at Figure 79, is that what you meant by "RC-like Curves" ??? Brian
