Problem with FSL, Dual Microblaze and Xilkernel.

Hi to all, 

 
I don't understand what is wrong with my design. Can someone give me an
idea ?
I design a dual microbleze with BSB ( EDK 11.5) :
Microblaze_0 + RS232_UART_1 + XPS_timer, 
Microblaze_1 + XPS_timer, 
Shared resources: Mutex, Shared_bram and DDR2_SDRAM.
After that, I exported hw design to SDK.
This it work ok with Xilkernel in SDK, but when I add a FSL conection
between the two microblaze, and I try to install Xilkernel in SDK on
Microblaze_0, I receive a strange error : 
 
Compiling standalone
Compiling common
Compiling lldma
mb-hw.c: In function 'int_system_init':
mb-hw.c:143: error: 'XPAR_XPS_INTC_2_DEVICE_ID' undeclared (first use in
this function)
mb-hw.c:143: error: (Each undeclared identifier is reported only once
mb-hw.c:143: error: for each function it appears in.)
mb-hw.c:150: error: 'XPAR_XPS_INTC_2_BASEADDR' undeclared (first use in
this function)

The XPS_intc2 is attached to Microblaze_1, but it gives me this error when
I compile Xilkernel for Microblaze_1 ?!?!
I don't receive this errors if I use Standalone SO in SDK ( this is because
Standalone don't use XPS_Timer ? )

I attached the mhs file.

Can someone give me an idea what is wrong?

 
Many thanks,

Iulian

#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 11.5 Build
EDK_LS5.70
# Wed Sep 15 11:28:27 2010
# Target Board:  Xilinx XUPV5-LX110T Evaluation Platform Rev A
# Family:    virtex5
# Device:    xc5vlx110t
# Package:   ff1136
# Speed Grade:  -1
# Processor number: 2
# Processor 1: microblaze_0
# System clock frequency: 125.0
# Debug Interface: On-Chip HW Debug Module
# Processor 2: microblaze_1
# System clock frequency: 125.0
# Debug Interface: On-Chip HW Debug Module
#
##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_pin, DIR
= O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin,
DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_CE_pin = fpga_0_DDR2_SDRAM_DDR2_CE_pin, DIR =
O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_CS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CS_n_pin,
DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR
= O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin,
DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin,
DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_DDR2_WE_n_pin,
DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin =
fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_DDR2_Addr_pin,
DIR = O, VEC = [12:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR =
IO, VEC = [63:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR =
O, VEC = [7:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR
= IO, VEC = [7:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin,
DIR = IO, VEC = [7:0]
 PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ
= 100000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST,
RST_POLARITY = 0


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_INTERCONNECT = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER HW_VER = 7.20.d
 PARAMETER C_FSL_LINKS = 1
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE SFSL0 = fsl_v20_1
 BUS_INTERFACE MFSL0 = fsl_v20_0
 PORT MB_RESET = mb_reset
 PORT INTERRUPT = microblaze_0_Interrupt
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = clk_125_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_125_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_125_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_1
 PARAMETER C_INTERCONNECT = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER HW_VER = 7.20.d
 PARAMETER C_FSL_LINKS = 1
 BUS_INTERFACE DPLB = mb_plb_1
 BUS_INTERFACE IPLB = mb_plb_1
 BUS_INTERFACE DEBUG = microblaze_1_mdm_bus
 BUS_INTERFACE DLMB = dlmb_1
 BUS_INTERFACE ILMB = ilmb_1
 BUS_INTERFACE SFSL0 = fsl_v20_0
 BUS_INTERFACE MFSL0 = fsl_v20_1
 PORT MB_RESET = mb_reset
 PORT INTERRUPT = microblaze_1_Interrupt
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb_1
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = clk_125_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb_1
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_125_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb_1
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = clk_125_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr_1
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb_1
 BUS_INTERFACE BRAM_PORT = dlmb_port_1
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr_1
 PARAMETER HW_VER = 2.10.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb_1
 BUS_INTERFACE BRAM_PORT = ilmb_port_1
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram_1
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port_1
 BUS_INTERFACE PORTB = dlmb_port_1
END

BEGIN xps_mutex
 PARAMETER INSTANCE = xps_mutex_0
 PARAMETER C_ASYNC_CLKS = 0
 PARAMETER HW_VER = 1.00.d
 PARAMETER C_SPLB0_BASEADDR = 0x82400000
 PARAMETER C_SPLB0_HIGHADDR = 0x8240ffff
 PARAMETER C_SPLB1_BASEADDR = 0x82600000
 PARAMETER C_SPLB1_HIGHADDR = 0x8260ffff
 BUS_INTERFACE SPLB0 = mb_plb
 BUS_INTERFACE SPLB1 = mb_plb_1
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_Uart_1_RX_pin
 PORT TX = fpga_0_RS232_Uart_1_TX_pin
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_0
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_BASEADDR = 0x83c00000
 PARAMETER C_HIGHADDR = 0x83c0ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Interrupt = xps_timer_0_Interrupt
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_1
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_BASEADDR = 0x83c00000
 PARAMETER C_HIGHADDR = 0x83c0ffff
 BUS_INTERFACE SPLB = mb_plb_1
 PORT Interrupt = xps_timer_1_Interrupt
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR2_SDRAM
 PARAMETER C_NUM_PORTS = 2
 PARAMETER C_NUM_IDELAYCTRL = 3
 PARAMETER C_IDELAYCTRL_LOC =
IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1
 PARAMETER C_MEM_PARTNO = mt4htf3264h-53e
 PARAMETER C_MEM_ODT_TYPE = 1
 PARAMETER C_MEM_CLK_WIDTH = 2
 PARAMETER C_MEM_ODT_WIDTH = 2
 PARAMETER C_MEM_CE_WIDTH = 2
 PARAMETER C_MEM_CS_N_WIDTH = 2
 PARAMETER C_DDR2_DQSN_ENABLE = 1
 PARAMETER C_PIM0_BASETYPE = 2
 PARAMETER C_PIM1_BASETYPE = 2
 PARAMETER HW_VER = 5.04.a
 PARAMETER C_MPMC_BASEADDR = 0x90000000
 PARAMETER C_MPMC_HIGHADDR = 0x9fffffff
 BUS_INTERFACE SPLB0 = mb_plb
 BUS_INTERFACE SPLB1 = mb_plb_1
 PORT MPMC_Clk0 = clk_125_0000MHzPLL0
 PORT MPMC_Clk0_DIV2 = clk_62_5000MHzPLL0
 PORT MPMC_Clk90 = clk_125_0000MHz90PLL0
 PORT MPMC_Clk_200MHz = clk_200_0000MHz
 PORT MPMC_Rst = sys_periph_reset
 PORT DDR2_Clk = fpga_0_DDR2_SDRAM_DDR2_Clk_pin
 PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin
 PORT DDR2_CE = fpga_0_DDR2_SDRAM_DDR2_CE_pin
 PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_DDR2_CS_n_pin
 PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin
 PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin
 PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin
 PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_DDR2_WE_n_pin
 PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin
 PORT DDR2_Addr = fpga_0_DDR2_SDRAM_DDR2_Addr_pin
 PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin
 PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin
 PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin
 PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = shared_bram_if_cntlr_0_top
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x8a008000
 PARAMETER C_HIGHADDR = 0x8a009fff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE PORTA = shared_bram_if_cntlr_0_bram_block_PortA
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = shared_bram_if_cntlr_0_bottom
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x8a008000
 PARAMETER C_HIGHADDR = 0x8a009fff
 BUS_INTERFACE SPLB = mb_plb_1
 BUS_INTERFACE PORTA = shared_bram_if_cntlr_0_bram_block_PortB
END

BEGIN bram_block
 PARAMETER INSTANCE = shared_bram_if_cntlr_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = shared_bram_if_cntlr_0_bram_block_PortA
 BUS_INTERFACE PORTB = shared_bram_if_cntlr_0_bram_block_PortB
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 125000000
 PARAMETER C_CLKOUT0_PHASE = 90
 PARAMETER C_CLKOUT0_GROUP = PLL0
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 125000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = PLL0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 200000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = NONE
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT3_FREQ = 62500000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = PLL0
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER HW_VER = 3.02.a
 PORT CLKIN = dcm_clk_s
 PORT CLKOUT0 = clk_125_0000MHz90PLL0
 PORT CLKOUT1 = clk_125_0000MHzPLL0
 PORT CLKOUT2 = clk_200_0000MHz
 PORT CLKOUT3 = clk_62_5000MHzPLL0
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
END

BEGIN mdm
 PARAMETER INSTANCE = mdm_0
 PARAMETER C_MB_DBG_PORTS = 2
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER HW_VER = 1.00.g
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb_1
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
 BUS_INTERFACE MBDEBUG_1 = microblaze_1_mdm_bus
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 2.00.a
 PORT Slowest_sync_clk = clk_125_0000MHzPLL0
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Dcm_locked = Dcm_all_locked
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Intr = xps_timer_0_Interrupt
 PORT Irq = microblaze_0_Interrupt
END

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_2
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = mb_plb_1
 PORT Intr = xps_timer_1_Interrupt
 PORT Irq = microblaze_1_Interrupt
END

BEGIN fsl_v20
 PARAMETER INSTANCE = fsl_v20_0
 PARAMETER HW_VER = 2.11.b
 PORT FSL_Clk = clk_125_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN fsl_v20
 PARAMETER INSTANCE = fsl_v20_1
 PARAMETER HW_VER = 2.11.b
 PORT FSL_Clk = clk_125_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END




	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Hi again,
 
Tha problem was the .mss file. There was there something mixed between the
two MicroBlazes. I modified the .mss file and the Xilkernel is compiling
correctly on both processors, but when I try to change some settings in
"Software Platform Settings" and press OK, the SDK  suddenly stops with
Eclipse message : "JVM terminated. Exit code=1". 
This problem does not appear when I use the same design but without FSL
connection. 
I can't manage to find if is it a bug or a problem in my design. Can
someone give me an ideea ? 
 
Many thanks,
Iulian	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com