I am listening to the Xilinx webinar on partial reconfiguration and they say the Artix 7 will be the first "spartan" type device that will be supported under the ISE software for partial reconfiguration. Anyone heard when the Artix 7 devices are supposed to be in production? Are we talking about a practical time frame such as 6 to 9 months or is it being stated as a year or more? Or have they only talked about when they will be shipping "samples"? I know there can be quite a difference.
Xilinx Artix 7 - When?
Started by ●October 5, 2010
Reply by ●October 5, 20102010-10-05
rickman <gnuarm@gmail.com> wrote:> I am listening to the Xilinx webinar on partial reconfiguration and > they say the Artix 7 will be the first "spartan" type device that will > be supported under the ISE software for partial reconfiguration. > Anyone heard when the Artix 7 devices are supposed to be in > production? Are we talking about a practical time frame such as 6 to > 9 months or is it being stated as a year or more? Or have they only > talked about when they will be shipping "samples"? I know there can > be quite a difference.Are you talking about some types in ES availability or about general availability? ES sample might be 9 month, GA much longer. Even S6 I wouldn't call general available... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by ●October 5, 20102010-10-05
I doubt they will be available in any numbers if at all in your practical timescales. Spartan-6 is the practical choice for that timescale given the availability has now improved vastly. As a time mark we are now heading towards 2 years since Spartan-6 was announced.and it is just being available in serious numbers now. John Adair Enterpoint Ltd. On 5 Oct, 20:43, rickman <gnu...@gmail.com> wrote:> I am listening to the Xilinx webinar on partial reconfiguration and > they say the Artix 7 will be the first "spartan" type device that will > be supported under the ISE software for partial reconfiguration. > Anyone heard when the Artix 7 devices are supposed to be in > production? =A0Are we talking about a practical time frame such as 6 to > 9 months or is it being stated as a year or more? =A0Or have they only > talked about when they will be shipping "samples"? =A0I know there can > be quite a difference.
Reply by ●October 5, 20102010-10-05
On Oct 5, 12:43=A0pm, rickman <gnu...@gmail.com> wrote:> I am listening to the Xilinx webinar on partial reconfiguration and > they say the Artix 7 will be the first "spartan" type device that will > be supported under the ISE software for partial reconfiguration. > Anyone heard when the Artix 7 devices are supposed to be in > production? =A0Are we talking about a practical time frame such as 6 to > 9 months or is it being stated as a year or more? =A0Or have they only > talked about when they will be shipping "samples"? =A0I know there can > be quite a difference.There is no announced date for Artix-7 device availability at this time. Ed McGettigan -- Xilinx Inc.
Reply by ●October 5, 20102010-10-05
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: ...> There is no announced date for Artix-7 device availability at this > time.Is there something announced for S6? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by ●October 5, 20102010-10-05
On Oct 5, 3:12=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote:> Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > ... > > > There is no announced date for Artix-7 device availability at this > > time. > > Is there something announced for S6? > > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar=mstadt.de> > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------With the exception of the XC6SLX4 and XC6SLX9 all devices are in production and in stock at Avnet for small quantities and 6-8 weeks times for larger quantities. http://avnetexpress.avnet.com/store/em/EMController?action=3Dproducts&N=3D0= &&term=3DXC6SLX Ed McGettigan -- Xilinx Inc.
Reply by ●October 6, 20102010-10-06
On Oct 5, 5:50 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:> On Oct 5, 12:43 pm, rickman <gnu...@gmail.com> wrote: > > > I am listening to the Xilinx webinar on partial reconfiguration and > > they say the Artix 7 will be the first "spartan" type device that will > > be supported under the ISE software for partial reconfiguration. > > Anyone heard when the Artix 7 devices are supposed to be in > > production? Are we talking about a practical time frame such as 6 to > > 9 months or is it being stated as a year or more? Or have they only > > talked about when they will be shipping "samples"? I know there can > > be quite a difference. > > There is no announced date for Artix-7 device availability at this > time.Ok, so if I understand what was said in the presentation today, there is no support for partial reconfiguration in any of the available Spartan devices, right? I remember looking into PR for quite a while some years back and had been told that Xilinx "was committed" to supporting PR in Spartan parts. That was literally 8 years ago. A lot of the presentation talked to the cost savings that was possible using PR. But that only makes sense to me if it can be used with low cost parts. Reducing the cost of using a more expensive part by using a complex process is a poor substitute to just using a part that costs less. But if I can use the less expensive part and cut my costs further by using PR, that can make a number of projects practical that otherwise wouldn't be. I don't even want to do "dynamic" PR, I just want to have the flexibility of configuring the modules when I configure the full part initially. Would that be "static" PR? This makes a huge difference in the exact scenario they described for a product with multiple interface modules, but the number of possible modules larger than just three. Instead of a 100,000 LUT Spartan, I would be able to use a 10,000 LUT device and have room to spare. This could be such a enabler of projects. Rick
Reply by ●October 6, 20102010-10-06
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote:> On Oct 5, 3:12�pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- > darmstadt.de> wrote: > > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > ... > > > > > There is no announced date for Artix-7 device availability at this > > > time. > > > > Is there something announced for S6? > >> With the exception of the XC6SLX4 and XC6SLX9 all devices are in > production and in stock at Avnet for small quantities and 6-8 weeks > times for larger quantities.> http://avnetexpress.avnet.com/store/em/EMController?action=products&N=0&&term=XC6SLXAny expected roll-out time for SLX4/SLX9? They are the only parts in QFP... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by ●October 6, 20102010-10-06
On 6 Okt., 07:06, rickman <gnu...@gmail.com> wrote: =A0A> lot of the presentation talked to the cost savings that was possible > using PR. =A0But that only makes sense to me if it can be used with low > cost parts. =A0Reducing the cost of using a more expensive part by using > a complex process is a poor substitute to just using a part that costs > less. =A0But if I can use the less expensive part and cut my costs > further by using PR, that can make a number of projects practical that > otherwise wouldn't be.I completely disagree. If you have a design that barely fits in a 6k$ part and can reduce the LUT count by a factor of 4 by using PR you save about 4k$ per chip This is what happens for DNA pattern matching machines. Try saving 4k$ with a spartan-3. The volume where saving 10$ per chip justifies the more complex PR design process is rather high. Kolja
Reply by ●October 8, 20102010-10-08
On Oct 6, 1:12 pm, Kolja Sulimma <ksuli...@googlemail.com> wrote:> On 6 Okt., 07:06, rickman <gnu...@gmail.com> wrote: > A > > > lot of the presentation talked to the cost savings that was possible > > using PR. But that only makes sense to me if it can be used with low > > cost parts. Reducing the cost of using a more expensive part by using > > a complex process is a poor substitute to just using a part that costs > > less. But if I can use the less expensive part and cut my costs > > further by using PR, that can make a number of projects practical that > > otherwise wouldn't be. > > I completely disagree. > If you have a design that barely fits in a 6k$ part and can reduce the > LUT > count by a factor of 4 by using PR you save about 4k$ per chip > This is what happens for DNA pattern matching machines. > > Try saving 4k$ with a spartan-3. > > The volume where saving 10$ per chip justifies the more complex PR > design process > is rather high.Yes, the designs that use a $10 chip ARE high volume apps. I've never seen a part that costs $6000, but I did see one that used a $1500 chip. The unit this was going in sold for $100,000 and they expected to sell much less than 100 per year. I remember that the initial design for that chip used less than 20% of the LUTs. Do you think they cared at all about using a tool like PR? I'm sure there are designs using Vertex chips (high cost) that would benefit from the PR. My point is that if PR were available for the low cost Spartan line, it would result in significant additional sales. Xilinx doesn't want to sell lower costs chips unless it somehow means more profit. The only way PR makes profit for them is if it sells chips they otherwise would not have sold. That makes much more sense at the low end than the high end. The real problem is that Xilinx doesn't "get" the low end. Yes, they will brag about some product where they sold a million Spartan chips without saying it required cutting their margin to under a buck, picking an imaginary example. But if PR makes a design feasible by cutting the part size they could have sold the cheaper chips at the same price with a two dollar margin yielding twice the total profit. Or better yet, design variations of their chips for the truly low end like Silicon Blue does. Xilinx thinks they can't make any worthwhile money at $2 a chip. Maybe they can't, but others will. Rick
