Hello all, I am presently working with a virtix 5 FPGA and trying to get the rocket IOs to work with reading in the data generated from my ADC. The ADC is clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and my data 4 bits transitioning at 250Mhz. I am then configuring the FPGA to store the data after it has been serial to parallel converted within the FPGA then I read it out later after it has taken the data so I can process my FFT in matlab. My problem is I know my ADC is working since I first took the data over a scope, but I want to speed up the measuring process by using a cool and fancy FPGA. My question is, can any help me in setting up the rocket IOs so ensure it does not miss any bits or transitions? If 1 in just 1000 samples it wrong my FFT is completely crap and I cant use it! My present setup, which I have no clue if I am correct, is I use the rockets to sync to the incoming data (250MHz bits) only ( not the output clock). I then use the same clock recovered for the data to then clock the data into memory. My question is, is there a better way to do this? Cant i use my 500MHz clock to just clock the other data rocket IOs or since the rocket IOs work off of a PLL, I cant do that..... I feel this must be a standard thing in using the rocket IOs... I just don't have any clue on the proper setup. If anyone could help that would be great! Jgk --------------------------------------- Posted through http://www.FPGARelated.com
Virtex 5 Rocket IO design for reading in ADC data.
Started by ●June 29, 2011
Reply by ●June 29, 20112011-06-29
>Hello all, > >I am presently working with a virtix 5 FPGA and trying to get the rocket >IOs to work with reading in the data generated from my ADC. The ADC is >clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and mydata>4 bits transitioning at 250Mhz. I am then configuring the FPGA to storethe>data after it has been serial to parallel converted within the FPGA thenI>read it out later after it has taken the data so I can process my FFT in >matlab. My problem is I know my ADC is working since I first took thedata>over a scope, but I want to speed up the measuring process by using acool>and fancy FPGA. My question is, can any help me in setting up the rocket >IOs so ensure it does not miss any bits or transitions? If 1 in just 1000 >samples it wrong my FFT is completely crap and I cant use it! > >My present setup, which I have no clue if I am correct, is I use the >rockets to sync to the incoming data (250MHz bits) only ( not the output >clock). I then use the same clock recovered for the data to then clockthe>data into memory. My question is, is there a better way to do this? Canti>use my 500MHz clock to just clock the other data rocket IOs or since the >rocket IOs work off of a PLL, I cant do that..... > >I feel this must be a standard thing in using the rocket IOs... I just >don't have any clue on the proper setup. If anyone could help that would >be great! > > > >Jgk > > > >--------------------------------------- >Posted through http://www.FPGARelated.com >I am slightly confused as you are talking about LVDS and Rocket IO which are not the same. Usually with ADC designs you would input the LVDS signals from the ADC into the FPGA and use the ISERDES block clocked from the ADC clock. You may also have to use some soft of calibartion scheme involving an IDELAY block to ensure all bits are synchronised. Jon --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●June 30, 20112011-06-30
Hello Jon, I have output LVDS drive on my asic chip which I am then interfacing to the rocket IOs of the FPGA. Sorry for the confusion. So you are saying thou that I should not try any clock recoverary but just the clock from my asic? Is there anything else I would need to know to get this working properly? Thanks so much Jgk>>Hello all, >> >>I am presently working with a virtix 5 FPGA and trying to get the rocket >>IOs to work with reading in the data generated from my ADC. The ADC is >>clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and my >data >>4 bits transitioning at 250Mhz. I am then configuring the FPGA to store >the >>data after it has been serial to parallel converted within the FPGA then >I >>read it out later after it has taken the data so I can process my FFT in >>matlab. My problem is I know my ADC is working since I first took the >data >>over a scope, but I want to speed up the measuring process by using a >cool >>and fancy FPGA. My question is, can any help me in setting up the rocket >>IOs so ensure it does not miss any bits or transitions? If 1 in just1000>>samples it wrong my FFT is completely crap and I cant use it! >> >>My present setup, which I have no clue if I am correct, is I use the >>rockets to sync to the incoming data (250MHz bits) only ( not the output >>clock). I then use the same clock recovered for the data to then clock >the >>data into memory. My question is, is there a better way to do this? Cant >i >>use my 500MHz clock to just clock the other data rocket IOs or since the >>rocket IOs work off of a PLL, I cant do that..... >> >>I feel this must be a standard thing in using the rocket IOs... I just >>don't have any clue on the proper setup. If anyone could help thatwould>>be great! >> >> >> >>Jgk >> >> >> >>--------------------------------------- >>Posted through http://www.FPGARelated.com >> > >I am slightly confused as you are talking about LVDS and Rocket IO which >are not the same. Usually with ADC designs you would input the LVDSsignals>from the ADC into the FPGA and use the ISERDES block clocked from the ADC >clock. You may also have to use some soft of calibartion scheme involving >an IDELAY block to ensure all bits are synchronised. > >Jon > >--------------------------------------- >Posted through http://www.FPGARelated.com >--------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●June 30, 20112011-06-30
>Hello Jon, > >I have output LVDS drive on my asic chip which I am then interfacing tothe>rocket IOs of the FPGA. Sorry for the confusion. So you are saying thou >that I should not try any clock recoverary but just the clock from myasic?> Is there anything else I would need to know to get this workingproperly?> >Thanks so much > >Jgk > > >>>Hello all, >>> >>>I am presently working with a virtix 5 FPGA and trying to get therocket>>>IOs to work with reading in the data generated from my ADC. The ADC is >>>clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and my >>data >>>4 bits transitioning at 250Mhz. I am then configuring the FPGA to store >>the >>>data after it has been serial to parallel converted within the FPGAthen>>I >>>read it out later after it has taken the data so I can process my FFTin>>>matlab. My problem is I know my ADC is working since I first took the >>data >>>over a scope, but I want to speed up the measuring process by using a >>cool >>>and fancy FPGA. My question is, can any help me in setting up therocket>>>IOs so ensure it does not miss any bits or transitions? If 1 in just >1000 >>>samples it wrong my FFT is completely crap and I cant use it! >>> >>>My present setup, which I have no clue if I am correct, is I use the >>>rockets to sync to the incoming data (250MHz bits) only ( not theoutput>>>clock). I then use the same clock recovered for the data to then clock >>the >>>data into memory. My question is, is there a better way to do this?Cant>>i >>>use my 500MHz clock to just clock the other data rocket IOs or sincethe>>>rocket IOs work off of a PLL, I cant do that..... >>> >>>I feel this must be a standard thing in using the rocket IOs... I just >>>don't have any clue on the proper setup. If anyone could help that >would >>>be great! >>> >>> >>> >>>Jgk >>> >>> >>> >>>--------------------------------------- >>>Posted through http://www.FPGARelated.com >>> >> >>I am slightly confused as you are talking about LVDS and Rocket IO which >>are not the same. Usually with ADC designs you would input the LVDS >signals >>from the ADC into the FPGA and use the ISERDES block clocked from theADC>>clock. You may also have to use some soft of calibartion schemeinvolving>>an IDELAY block to ensure all bits are synchronised. >> >>Jon >> >>--------------------------------------- >>Posted through http://www.FPGARelated.com >> > >--------------------------------------- >Posted through http://www.FPGARelated.com >I am even more confused now as first you say you have an ADC and now you say an ASIC. I think you need to specify exactly what you have. Is it an ADC from say TI or is it a custom ASIC chip? Rocket IO do not even use LVDS type signals so I dont really see what you are trying to do. Jon --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●June 30, 20112011-06-30
Hello Jon, I designed a custom ASIC sigma delta ADC and i do not decimate on chip. so thus my data is coming out on 4 bits at 250MHz (clocked at 500MHz). On my ASIC, i designed custom 1.2V LVDS drivers that need a 100ohm termination off chip. I am using the rocket IOs and terminating them internally by programming them to have 100Ohm termination. I then set the rocket IOs to be lvds standard inputs.... which I think is correct to read in my data. I have to use the rocket IOs since my data is at 250MHz.....clocked at 500Mhz.. Am I doing anything wrong here? What type of signals would you normally use rocket IOs at... and even at high data rates.... I would think lvds type signals... Now what i think i am having trouble with is setting up the syncing... Is that alittle bit more clear? Jgk>>Hello Jon, >> >>I have output LVDS drive on my asic chip which I am then interfacing to >the >>rocket IOs of the FPGA. Sorry for the confusion. So you are saying thou >>that I should not try any clock recoverary but just the clock from my >asic? >> Is there anything else I would need to know to get this working >properly? >> >>Thanks so much >> >>Jgk >> >> >>>>Hello all, >>>> >>>>I am presently working with a virtix 5 FPGA and trying to get the >rocket >>>>IOs to work with reading in the data generated from my ADC. The ADC is >>>>clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and my >>>data >>>>4 bits transitioning at 250Mhz. I am then configuring the FPGA tostore>>>the >>>>data after it has been serial to parallel converted within the FPGA >then >>>I >>>>read it out later after it has taken the data so I can process my FFT >in >>>>matlab. My problem is I know my ADC is working since I first took the >>>data >>>>over a scope, but I want to speed up the measuring process by using a >>>cool >>>>and fancy FPGA. My question is, can any help me in setting up the >rocket >>>>IOs so ensure it does not miss any bits or transitions? If 1 in just >>1000 >>>>samples it wrong my FFT is completely crap and I cant use it! >>>> >>>>My present setup, which I have no clue if I am correct, is I use the >>>>rockets to sync to the incoming data (250MHz bits) only ( not the >output >>>>clock). I then use the same clock recovered for the data to then clock >>>the >>>>data into memory. My question is, is there a better way to do this? >Cant >>>i >>>>use my 500MHz clock to just clock the other data rocket IOs or since >the >>>>rocket IOs work off of a PLL, I cant do that..... >>>> >>>>I feel this must be a standard thing in using the rocket IOs... I just >>>>don't have any clue on the proper setup. If anyone could help that >>would >>>>be great! >>>> >>>> >>>> >>>>Jgk >>>> >>>> >>>> >>>>--------------------------------------- >>>>Posted through http://www.FPGARelated.com >>>> >>> >>>I am slightly confused as you are talking about LVDS and Rocket IOwhich>>>are not the same. Usually with ADC designs you would input the LVDS >>signals >>>from the ADC into the FPGA and use the ISERDES block clocked from the >ADC >>>clock. You may also have to use some soft of calibartion scheme >involving >>>an IDELAY block to ensure all bits are synchronised. >>> >>>Jon >>> >>>--------------------------------------- >>>Posted through http://www.FPGARelated.com >>> >> >>--------------------------------------- >>Posted through http://www.FPGARelated.com >> > >I am even more confused now as first you say you have an ADC and now you >say an ASIC. I think you need to specify exactly what you have. Is it an >ADC from say TI or is it a custom ASIC chip? Rocket IO do not even useLVDS>type signals so I dont really see what you are trying to do. > >Jon > >--------------------------------------- >Posted through http://www.FPGARelated.com >--------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●June 30, 20112011-06-30
>Hello Jon, > >I designed a custom ASIC sigma delta ADC and i do not decimate on chip.so>thus my data is coming out on 4 bits at 250MHz (clocked at 500MHz). Onmy>ASIC, i designed custom 1.2V LVDS drivers that need a 100ohm termination >off chip. I am using the rocket IOs and terminating them internally by >programming them to have 100Ohm termination. I then set the rocket IOsto>be lvds standard inputs.... which I think is correct to read in my data.I>have to use the rocket IOs since my data is at 250MHz.....clocked at >500Mhz.. Am I doing anything wrong here? What type of signals would you >normally use rocket IOs at... and even at high data rates.... I wouldthink>lvds type signals... Now what i think i am having trouble with issetting>up the syncing... > >Is that alittle bit more clear? >You would normally use Rocket IO for signals that are in the GHz range. LVDS on a Virtex 5 would easily handle a 250 MHz signal. Take a look at the Xilinx website as they have some application notes on interfacing ADCs. You do not want to be using Rocket IO for this type of application. Jon --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●June 30, 20112011-06-30
Hello Jon, So I do understand that 250MHz isn't fast, and the rocket IOs operate up to 3+GHz. The reason why I am using the rocket IOs now is because my next ASIC will be clocked at 1GHz to 1.5GHz.... So I was thinking if I can get the rocket ios working at 250MHz it should be problem reprogramming them to a higher rate. When you say that LVDS on the virtex 5 could easily be handled at 250MHz would I then need a core clock at above 250MHz? Also what is hte max LVDS could be used on the virtex 5 without the rocket IOs? Can i use LVDS at 1GHz? Jgk>You would normally use Rocket IO for signals that are in the GHz range. >LVDS on a Virtex 5 would easily handle a 250 MHz signal. Take a look atthe>Xilinx website as they have some application notes on interfacing ADCs.You>do not want to be using Rocket IO for this type of application. > >Jon > >--------------------------------------- >Posted through http://www.FPGARelated.com >--------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●June 30, 20112011-06-30
>Hello Jon, > >So I do understand that 250MHz isn't fast, and the rocket IOs operate upto>3+GHz. The reason why I am using the rocket IOs now is because my nextASIC>will be clocked at 1GHz to 1.5GHz.... So I was thinking if I can get the >rocket ios working at 250MHz it should be problem reprogramming them to a >higher rate. > >When you say that LVDS on the virtex 5 could easily be handled at 250MHz >would I then need a core clock at above 250MHz? Also what is hte maxLVDS>could be used on the virtex 5 without the rocket IOs? Can i use LVDS at >1GHz? > >JgkIt seem to me as though you dont really understand the Virtex 5 architecture. You need to read the user guide and data sheet to get a feel what is possible with a certain IO technology. Rocket IO uses CML type drivers which are different to LVDS. LVDS upto 1.25 Gb/s is possible. Jon --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●June 30, 20112011-06-30
Hello Jon, You are completely correct, I do not understand the virtex 5 at all!! What guide(since there are like 10) would you recommend reading to learn about LVDS. Thank god i pinned out almost everything on my PCB to headers... just need to make a new socket board! Thanks Jgk> >It seem to me as though you dont really understand the Virtex 5 >architecture. You need to read the user guide and data sheet to get afeel>what is possible with a certain IO technology. Rocket IO uses CML type >drivers which are different to LVDS. LVDS upto 1.25 Gb/s is possible. > >Jon > >--------------------------------------- >Posted through http://www.FPGARelated.com >--------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●June 30, 20112011-06-30
>Hello Jon, > >You are completely correct, I do not understand the virtex 5 at all!! >What guide(since there are like 10) would you recommend reading to learn >about LVDS. Thank god i pinned out almost everything on my PCB to >headers... just need to make a new socket board! > >Thanks > >Jgk >> >>It seem to me as though you dont really understand the Virtex 5 >>architecture. You need to read the user guide and data sheet to get a >feel >>what is possible with a certain IO technology. Rocket IO uses CML type >>drivers which are different to LVDS. LVDS upto 1.25 Gb/s is possible. >> >>Jon >> >>--------------------------------------- >>Posted through http://www.FPGARelated.com >> > >--------------------------------------- >Posted through http://www.FPGARelated.com >Just go to the Virtex 5 documentation page. There is the User Guide which will give you info about all the tech inside the fpga. The data sheet will tell you how fast things can go. I have just had a look on Xilinx and there is an app note called Virtex-5 FPGA Interface to a JESD204A Compliant ADC It looks like you can use Rocket IO if your ADC is compliant to JESD204A standard. But as you have LVDS signals then you cant use this method. Jon --------------------------------------- Posted through http://www.FPGARelated.com
