Jian Xu (@elliotxu)
To me, the design in FPGA on one side should be 4 Serdes RX block, some glue logic (e.g. FIFO) and 1 Serdes TX block. The glue logic takes care of the format you...
You should be able to find I/O speed for both differential and single-ended from datasheet. If your ADC output is differential, 760MHz may be doable. V7 FPGA can...
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