Jian Xu (@elliotxu)

Jian Xu received the B.S. degree in electrical engineering from Shanghai Jiaotong University in 2004 and M.S. degree in electrical engineering from University of Cincinnati in 2007. Since 2007, he has been working in Maxlinear and Qualcomm as system engineer and bench test engineer to develop state-of-the-art IC emulation and test solution based on FPGA. His current interest is algorithm implementation and microprocessor-based system architecture in FPGA.

To me, the design in FPGA on one side should be 4 Serdes RX block, some glue logic (e.g. FIFO) and 1 Serdes TX block. The glue logic takes care of the format you...

Re: sampling 800mbps data in virtex 5QV

Reply posted 7 years ago (02/28/2017)
You should be able to find I/O speed for both differential and single-ended from datasheet. If your ADC output is differential, 760MHz may be doable. V7 FPGA can...

Re: Packaging custom IP (master) in XPS

Reply posted 7 years ago (02/08/2017)

Re: Best method for a large dot vector

Reply posted 8 years ago (03/05/2016)

Use this form to contact elliotxu

Before you can contact a member of the *Related Sites:

  • You must be logged in (register here)
  • You must confirm you email address