Would anyone have advice/guidance for myself in how to create a board taking 4 serial streams (think HDMI/DVI) and serialise them to send over one link (single 10G fiber via SFP+'s) to another FPGA that takes the link and parallelise it.
For simplicity consider a DVI Quad Link which has 12 channel Synchronous streams with a 120 bit interface and clock. It is possible to encapsulate the pixel and control in an IP/UDP (Internet protocol/User Datagram Protocol) frame and create a 10 G Ethernet fibre link in an FPGA and use SFP+ module to transmit video. At the receiver the streams could be reconstructed and drive TMDS encoders. You would have to build a set of 2 modules with FPGAs a Transmitter and a Receiver. I am curious, where is the need for such modules ?
To me, the design in FPGA on one side should be 4 Serdes RX block, some glue logic (e.g. FIFO) and 1 Serdes TX block. The glue logic takes care of the format you want to combine 4 serial streams (HDMI/DVI) into one serilaized stream (10G fiber). The other side is vice versa.