John Eaton (@jt_eaton)

Retired Asic designer from Hewlett Packard. Now consulting in design methods

Re: Covid-19 Stories

Reply posted 4 years ago (03/29/2020)
I'm taking this seriously. I've seen the numbers and I know how exponential curves work. My wife and I are both in the high risk group and stand a serious chance...

Re: Some doubt about reset bridge

Reply posted 5 years ago (08/07/2019)
If the reset signal deasserts near the clk edge then the first flop may not settle to a valid level before the next clock edge causing the second flop to also go...

Re: Guidelines for porting ASIC RTL to FPGA

Reply posted 7 years ago (04/11/2017)
You do not port asic code to an FPGA. Design is a two step process, you first enter and test the logic that you want and then you target it to the technology that...
Remember that Digital design consists of creating leaf level components and then configuring and interconnecting them into a design. Component designers do the former...

Re: Code review. Newbie's first verilog module!

Reply posted 8 years ago (03/23/2016)
I won't comment on the functionality but here are some suggestions for making your module more reusable.module iButton(Never hard code constants in a program. Always...

Re: Exploring adders: carry select adder any benefits?

Reply posted 8 years ago (02/19/2016)
All of this changes when you write code for an Asic. In today's processes you lay out a ripple-carry adder and you minimize the carry chain length by packing it...

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