Hi, I'm trying to process a Ethernet type package. Suppose if i have detected SFD and now have a

Hi, I'm trying to process a Ethernet type package. Suppose if i have detected SFD and now have a

I'm trying to decide on which to use for a project as the main default that may include a number of freelance people. can you say which of...

I'm trying to decide on which to use for a project as the main default that may include a number of freelance people. can you say which of these you actually use (the most) and have the best skills in Verilog systemVerilog SystemC VHDL Other And if possible what type of work you use it for in general I dont need to know why you use a particular one - and to avoid flame wars ...

What are thoughts on these two vendors goods? I like that they have cheap(er) PCIe options. My intended use case is to learn about HW and...

What are thoughts on these two vendors goods? I like that they have cheap(er) PCIe options. My intended use case is to learn about HW and HDL development with an existing strong OS development background so I want to write device drivers to interface etc. Right now I'm leaning toward Lattice but I like that Microsemi is embracing RISC-V.

Hi, I have been away from in-depth FPGA development for maybe a decade! I am looking to design an embedded camera product where power use is key....

Hi, I have been away from in-depth FPGA development for maybe a decade! I am looking to design an embedded camera product where power use is key. I'd like to use an FPGA for some video manipulation not much. I used to only use Altera FPGAs, so I know their architecture well enough. It looks like the Cyclone 10 LP is the lowest-power device they have, and their LE structure looks the same as when...

Does the Zynq7000 family contain any stored charge circuitry on the chip? The manual says there is "On-chip boot ROM", but is it mask-programmed...

Does the Zynq7000 family contain any stored charge circuitry on the chip? The manual says there is "On-chip boot ROM", but is it mask-programmed or flash? If there are flash cells, then what other SRAM-only ARM+FPGA chips should I look at? Best regards, Piotr

Last time I had to prepare a firmware for FPGA, that contained a complex hierarchy of blocks and subbblocks, containing registers and arrays of...

Last time I had to prepare a firmware for FPGA, that contained a complex hierarchy of blocks and subbblocks, containing registers and arrays of registers on different levels of hierarchy. Those registers were connected to simple block driven by IPbus ( https://github.com/ipbus/ipbus-firmware ) or AXI-Lite slave (e.g., generated with Tools/Create and Package New IP/Ctreate AXI4 Peripheral), that pr...

Hi, I want to interface on board ADC to spartan 3E startkit. Actually I am developing digital filter in FPGA for that I need ADC and...

Hi, I want to interface on board ADC to spartan 3E startkit. Actually I am developing digital filter in FPGA for that I need ADC and DAC interface with Spartan 3E. I have done with DAC but now I want to interface amplifier and ADC which are on board in Spartan 3E starter kit .........If any one have it's VHDL or Verilog code please give me..........Even I have find a document for imp...

Hi all, I would like to create and distribute a master clock and sync pulses to a number of boxes throughout a system. There will be some skew...

Hi all, I would like to create and distribute a master clock and sync pulses to a number of boxes throughout a system. There will be some skew between the signals, of unknown sign. Probably the clock will be 24.576MHz and sync will be in the kHz range. At the receiving nodes the clocks have to be de-jittered and preferably the two (or more) signals aligned with each other.

Hi, A wive-pipelined circuit has the same logic as its pipeline counterpart exc= ept that the wive-pipelined circuit has only one stage, a...

Hi, A wive-pipelined circuit has the same logic as its pipeline counterpart exc= ept that the wive-pipelined circuit has only one stage, a critical path fro= m the input register passing through a piece of computational logic to the = output register, and no intermediate registers. My invention kernel idea is: A designer provides the least information and = logic code about the critical ...

Hello everybody, and Happy New Year 2018! I am new to digital design, here are some basic questions: In particular for algorithm...

Hello everybody, and Happy New Year 2018! I am new to digital design, here are some basic questions: In particular for algorithm acceleration (e.g. arithmetic, cryptography, etc.), does it make sense to think both FPGA and ASIC when writing HDL library code? And, about pipelining combinational logic, what maximum gate-delay granularity would be good (for fmax) on FPGAs? I am guessing...