Quartus II - Disabling the Optimizer to use gate delay

Does anybody know how can I disable the automatic optimizer in Quartus II
to prevent it from eliminating redundant gates ?

(I am trying to implement a delay line using a cascade of inverters, which 
Quartus removes during compilation since they are logically redundant.)

thanks,

vbishtei@hotmail.com (vadim) wrote in message news:<2a613f5d.0406170517.611ae93c@posting.google.com>...
> Does anybody know how can I disable the automatic optimizer in Quartus II
> to prevent it from eliminating redundant gates ?
> 
> (I am trying to implement a delay line using a cascade of inverters, which 
> Quartus removes during compilation since they are logically redundant.)
> 
> thanks,

Hi Vadim,

Building delay chains is not recommended. You can use LCELL buffer as
shown below to force a route through two lcells.

module test (in,out);
input in;
output out;
wire lcaout;
lcell lca (in,lcaout);
lcell lcb (lcaout,out);
endmodule

Hope this helps.

Subroto Datta
Altera Corp.

Hello Vadim,

In VHDL, enter the following:

signal delay_gate : std_logic;
attribute keep    : boolean;
attribute keep of lval_rowdel_delaln 	: signal is true;

Similar construct exists for Verilog.

This turns delay_gate into an LCELL of whatever is feeding it. Quartus
doesn't remove LCELLs, unless Remove Redundant Logic Cells is set in
your design, which by default it is off - check your .qsf or under
Assignments/Settings/Analysis&Synth/More Settings.

If you want to keep a redundant register, set
REMOVE_DUPLICATE_REGISTERS to OFF for that register.

HTH, 

-- Pete

vbishtei@hotmail.com (vadim) wrote in message news:<2a613f5d.0406170517.611ae93c@posting.google.com>...
> Does anybody know how can I disable the automatic optimizer in Quartus II
> to prevent it from eliminating redundant gates ?
> 
> (I am trying to implement a delay line using a cascade of inverters, which 
> Quartus removes during compilation since they are logically redundant.)
> 
> thanks,

Oops cut and paste error ... my other msg should read:

attribute keep of delay_gate	: signal is true;

-- Pete

vbishtei@hotmail.com (vadim) wrote in message news:<2a613f5d.0406170517.611ae93c@posting.google.com>...
> Does anybody know how can I disable the automatic optimizer in Quartus II
> to prevent it from eliminating redundant gates ?
> 
> (I am trying to implement a delay line using a cascade of inverters, which 
> Quartus removes during compilation since they are logically redundant.)
> 
> thanks,