Forums

IP Coregen: FFT v2.1 IP core regd.

Started by anand August 24, 2004
Hi,

In my design, I am using the FFT v2.1 IP core thats available in the
IP Core generator that comes along with Xilinx ISE 6.2. I want to use
the scaling option (SCALE_SCH). I dont know how to derive the scaling
schedule. I am configuring the IP core to do 64 point FFT with 8-bit
inputs.

Any pointers or suggestions is highly appreciated.

Thanks.

Sincerely,
Anand