Advice to a newbie

On 5/27/2016 1:00 PM, Cecil Bayona wrote:
> I a retired person with limited resources and I've always been
> interested in CPU design, so now that I have time I wanted to give it a
> go using FPGAs to design simple CPUs.
>
> I would like some advice on several topics, one being which HDL language
> to learn first, although Verilog seems simpler I've read articles that
> encourages beginners to start with VHDL, although it seems more wordy, I
> believe it will help eliminate more dumb mistakes so I'm leaning that
> way. What is your advice?
>
> Another is which logic families/companies make products that are
> inexpensive and have good features useful in creating CPUs and DSP type
> products as I also am interested in Software Defined Radios.
>
> I have purchase for a starter kit a Lattice Brevia2 kit as it was
> inexpensive and has low power consumption, so I assume will be easier to
> use in the beginning. It's a simple device with 5K LUTs which seems to
> be enough for some of the simple processors that I'm interested in to
> start with, CPUs such as the J1 for starters. From some time back I've
> have a Xilinx Spartan 3 Started kit that I have not used, I plan to use
> it later for more complex designs.
>
> Your opinions and advice is welcomed.

I have been doing a lot of research and have come up with a plan.

I have already implemented the ep8080, a high efficiency I8080 CPU a 
processor that I worked with for many years in my line of work, we 
quickly converted to the I8085 since it's hardware was more efficient, 
and could run at a much higher clock rate. In any case I'm ready to move on.

After some deliberation and tool searching, I have decided to implement 
C H Tings ep32 processor as the next CPU, there are several reasons why, 
some are below;

1. It's a simple tested 32 bit Forth CPU, something I desire, not a work 
in progress.
2. It's implemented on a Brevia2 board, which I already own.
3. I have quite a bit of documentation on it, supplied by C H Ting, and 
it's quite good.
4. I have a Forth assembler, and compiler that generates machine code, 
with documentation.
5. I have the source to a resident eForth compiler for the CPU, with 
documentation.
6. It is written in VHDL which is the first language I want to learn.
7. I has room in the opcodes to add many new instructions.
8. It can pack multiple instructions in an instruction word to make it 
more efficient.
9. Large address space so I could use the external RAM to add program space.

So there are a lot of advantages in the design with room for me to add 
instructions, and make architectural changes. I will start trying to get 
it working this evening after I get all my day activities all done. I've 
setup a virtual W7 partition with VMware Player 12, with all the 
development software and it all seems to work just fine, including the 
serial port working fine at 115K baud rate.

The ep16 is next in the short future after that then the J1, and maybe 
the PDP11, and who knows what else. Before I move to some of these 
processors I need to become more familiar with VHDL as some of these 
CPUs such as the PDP11 with be implemented from scratch.

Let the fun begin.

-- 
Cecil - k5nwa

On 6/10/2016 2:05 PM, Cecil Bayona wrote:
>
> The ep16 is next in the short future after that then the J1, and maybe
> the PDP11, and who knows what else. Before I move to some of these
> processors I need to become more familiar with VHDL as some of these
> CPUs such as the PDP11 with be implemented from scratch.
>
> Let the fun begin.

VHDL is not so hard.  Just learn how to infer a register and instantiate 
a module and you are practically done.  The rest is just logic which can 
be added to the register code or inferred separately.  Life will be 
easier if you enable VHDL-2008 in your tools and use those features.

If you have any questions you can ask here or maybe comp.lang.vhdl would 
be good too.

-- 

Rick C

On 6/10/2016 3:54 PM, rickman wrote:
> On 6/10/2016 2:05 PM, Cecil Bayona wrote:
>>
>> The ep16 is next in the short future after that then the J1, and maybe
>> the PDP11, and who knows what else. Before I move to some of these
>> processors I need to become more familiar with VHDL as some of these
>> CPUs such as the PDP11 with be implemented from scratch.
>>
>> Let the fun begin.
>
> VHDL is not so hard.  Just learn how to infer a register and instantiate
> a module and you are practically done.  The rest is just logic which can
> be added to the register code or inferred separately.  Life will be
> easier if you enable VHDL-2008 in your tools and use those features.
>
> If you have any questions you can ask here or maybe comp.lang.vhdl would
> be good too.
>
I will today be starting on the ep32 CPU, later when I get back from 
running errands.

I setup a virtual Windows 7 PC and have Lattice Diamond and other tools 
loaded and working. I even have the serial port on the Brevia2 board 
running at 115K baud rate so all is ready. I posted about it on this 
topic earlier today.

Thanks for all the advice, and I will post in the c.l.vhdl when I have 
an issue with not understanding a feature of VHDL. So far looking at 
some books it all seems OK but a lot of details to remember.

-- 
Cecil - k5nwa

On Fri, 10 Jun 2016 16:11:09 -0500, Cecil Bayona wrote:

> On 6/10/2016 3:54 PM, rickman wrote:
>> On 6/10/2016 2:05 PM, Cecil Bayona wrote:
>>>
>>> The ep16 is next in the short future after that then the J1, and maybe
>>> the PDP11, and who knows what else. Before I move to some of these
>>> processors I need to become more familiar with VHDL as some of these
>>> CPUs such as the PDP11 with be implemented from scratch.
>>>
>>> Let the fun begin.
>>
>> VHDL is not so hard.  Just learn how to infer a register and
>> instantiate a module and you are practically done.  The rest is just
>> logic which can be added to the register code or inferred separately. 
>> Life will be easier if you enable VHDL-2008 in your tools and use those
>> features.
>>
>> If you have any questions you can ask here or maybe comp.lang.vhdl
>> would be good too.
>>
> I will today be starting on the ep32 CPU, later when I get back from
> running errands.
> 
> I setup a virtual Windows 7 PC and have Lattice Diamond and other tools
> loaded and working. I even have the serial port on the Brevia2 board
> running at 115K baud rate so all is ready. I posted about it on this
> topic earlier today.
> 
> Thanks for all the advice, and I will post in the c.l.vhdl when I have
> an issue with not understanding a feature of VHDL. So far looking at
> some books it all seems OK but a lot of details to remember.

I don't even try to remember all the details of C++ (which is my main 
computer language).  I just remember what's possible, and enough terms 
that I can use a book with a good index, or a site with a good search 
engine, and look up what I need to know.

Then I use it, then I forget it again.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

I'm looking for work -- see my website!