On 6/3/2016 1:09 PM, Rick C. Hodgin wrote:> On Friday, June 3, 2016 at 12:00:52 PM UTC-4, Rick C. Hodgin wrote: > > Received: > > http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/LatticeXP2Brevia2DevelopmentKit.aspx > > I am wanting to apply logic to this LED process, but I'm thinking there may > be some analog issues that I need to consider. For example, when a button > on the board is clicked, I assume there is some jitter time, such that if it > were sampled at a MHz frequency it would record jittery on/off signals for > a ms or two until the contact was made solid, and the same for releasing. > > As such, any logic which samples the buttons, for example, must include > things like identifying the first high signal, and then either sampling > the high/low ratio over periods of time to determine if it's still high > or low, and then using that value after the sampling period has expired, > or wait until the high signal persists solidly for something like 10ms, > and then consider that to be a single press event, and then wait for it > to go low again for something like 10ms before concluding it is actually > a release event. >> > Best regards, > Rick C. Hodgin >I like that board, you can implement simple CPUs in it for a low cost. This is a link to a video of FPGAs, this one is lesson 1, on lesson 2 they take a button and debounce it, the purpose of the project is to count a series of pulses on the LED based on pushing a button. -- Cecil - k5nwa
Advice to a newbie
Started by ●May 27, 2016
Reply by ●June 3, 20162016-06-03
Reply by ●June 3, 20162016-06-03
On Friday, June 3, 2016 at 3:02:24 PM UTC-4, Cecil Bayona wrote:> On 6/3/2016 1:09 PM, Rick C. Hodgin wrote: > > On Friday, June 3, 2016 at 12:00:52 PM UTC-4, Rick C. Hodgin wrote: > > Received: > > http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/LatticeXP2Brevia2DevelopmentKit.aspx > > > > I am wanting to apply logic to this LED process, but I'm thinking there may > > be some analog issues that I need to consider. For example, when a button > > on the board is clicked, I assume there is some jitter time, such that if it > > were sampled at a MHz frequency it would record jittery on/off signals for > > a ms or two until the contact was made solid, and the same for releasing. > > > > As such, any logic which samples the buttons, for example, must include > > things like identifying the first high signal, and then either sampling > > the high/low ratio over periods of time to determine if it's still high > > or low, and then using that value after the sampling period has expired, > > or wait until the high signal persists solidly for something like 10ms, > > and then consider that to be a single press event, and then wait for it > > to go low again for something like 10ms before concluding it is actually > > a release event. > > I like that board, you can implement simple CPUs in it for a low cost. > > This is a link to a video of FPGAs, this one is lesson 1, on lesson 2 > they take a button and debounce it, the purpose of the project is to > count a series of pulses on the LED based on pushing a button. > > -- > Cecil - k5nwaSpecs: http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/JL/LatticeXP2Brevia2DevelopmentKitUsersGuide.PDF?document_id=43735 In looking at the specs, it shows that all five momentary push buttons are already debounced, and 3 of the 4 DIP switches are (4 to 5 is not, pin 55). Awesome. Should make it easier. What are pins 142, 143, 144 (SRAM_CSb, SRAM_OEb, SRAM_WEb). I assume output enable and write enable? But what is CS? Some kind of strobe? Do the address and data pins go high, and write goes high, and then it's strobed before it actually writes? Or address pins go high, and then output goes high, and then it's strobed before data pins are ready? Or does CS signal when the operation is complete after OE or WE go high? Or are they something else entirely? :-) Best regards, Rick C. Hodgin
Reply by ●June 3, 20162016-06-03
On 6/3/2016 2:29 PM, Rick C. Hodgin wrote:> On Friday, June 3, 2016 at 3:02:24 PM UTC-4, Cecil Bayona wrote: >> On 6/3/2016 1:09 PM, Rick C. Hodgin wrote: >>> On Friday, June 3, 2016 at 12:00:52 PM UTC-4, Rick C. Hodgin wrote: >>> Received: >>> http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/LatticeXP2Brevia2DevelopmentKit.aspx >>> >>> I am wanting to apply logic to this LED process, but I'm thinking there may >>> be some analog issues that I need to consider. For example, when a button >>> on the board is clicked, I assume there is some jitter time, such that if it >>> were sampled at a MHz frequency it would record jittery on/off signals for >>> a ms or two until the contact was made solid, and the same for releasing. >>> >>> As such, any logic which samples the buttons, for example, must include >>> things like identifying the first high signal, and then either sampling >>> the high/low ratio over periods of time to determine if it's still high >>> or low, and then using that value after the sampling period has expired, >>> or wait until the high signal persists solidly for something like 10ms, >>> and then consider that to be a single press event, and then wait for it >>> to go low again for something like 10ms before concluding it is actually >>> a release event. >> >> I like that board, you can implement simple CPUs in it for a low cost. >> >> This is a link to a video of FPGAs, this one is lesson 1, on lesson 2 >> they take a button and debounce it, the purpose of the project is to >> count a series of pulses on the LED based on pushing a button. >> >> -- >> Cecil - k5nwa > > Specs: > > http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/JL/LatticeXP2Brevia2DevelopmentKitUsersGuide.PDF?document_id=43735 > > In looking at the specs, it shows that all five momentary push buttons > are already debounced, and 3 of the 4 DIP switches are (4 to 5 is not, > pin 55). > > Awesome. Should make it easier. > > What are pins 142, 143, 144 (SRAM_CSb, SRAM_OEb, SRAM_WEb). I assume > output enable and write enable? But what is CS? Some kind of strobe? > Do the address and data pins go high, and write goes high, and then > it's strobed before it actually writes? Or address pins go high, and > then output goes high, and then it's strobed before data pins are > ready? Or does CS signal when the operation is complete after OE or > WE go high? > > Or are they something else entirely? :-) > > Best regards, > Rick C. Hodgin >I would not be sure that applies to any application but is what the demo does, as they do not know what you will end up doing with the I/O pins. -- Cecil - k5nwa
Reply by ●June 3, 20162016-06-03
On Friday, June 3, 2016 at 3:42:54 PM UTC-4, Cecil Bayona wrote:> On 6/3/2016 2:29 PM, Rick C. Hodgin wrote: > > Specs: > > > > http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/JL/LatticeXP2Brevia2DevelopmentKitUsersGuide.PDF?document_id=43735 > > > > In looking at the specs, it shows that all five momentary push buttons > > are already debounced, and 3 of the 4 DIP switches are (4 to 5 is not, > > pin 55). > > > > Awesome. Should make it easier. > > > > What are pins 142, 143, 144 (SRAM_CSb, SRAM_OEb, SRAM_WEb). I assume > > output enable and write enable? But what is CS? Some kind of strobe? > > Do the address and data pins go high, and write goes high, and then > > it's strobed before it actually writes? Or address pins go high, and > > then output goes high, and then it's strobed before data pins are > > ready? Or does CS signal when the operation is complete after OE or > > WE go high? > > > > Or are they something else entirely? :-) > > I would not be sure that applies to any application but is what the demo > does, as they do not know what you will end up doing with the I/O pins.I think it's chip select. It looks like there are 17 address pins. 2^17 yields 128 KB. The data reads/writes are 8-bits each, so I presume I will be reading/writing 8 bits at that byte-address. 2^17 * 8 = 1 MBit. The specs say it has 2 MBit of SRAM, so I assume CS means chip select, and could be thought of essentially as the 18th address pin? I couldn't find the video with the lessons. Do you have a link, Cecil? Best regards, Rick C. Hodgin
Reply by ●June 3, 20162016-06-03
On 6/3/2016 2:46 PM, Rick C. Hodgin wrote:> On Friday, June 3, 2016 at 3:42:54 PM UTC-4, Cecil Bayona wrote: >> On 6/3/2016 2:29 PM, Rick C. Hodgin wrote: >>> Specs: >>> >>> http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/JL/LatticeXP2Brevia2DevelopmentKitUsersGuide.PDF?document_id=43735 >>> >>> In looking at the specs, it shows that all five momentary push buttons >>> are already debounced, and 3 of the 4 DIP switches are (4 to 5 is not, >>> pin 55). >>> >>> Awesome. Should make it easier. >>> >>> What are pins 142, 143, 144 (SRAM_CSb, SRAM_OEb, SRAM_WEb). I assume >>> output enable and write enable? But what is CS? Some kind of strobe? >>> Do the address and data pins go high, and write goes high, and then >>> it's strobed before it actually writes? Or address pins go high, and >>> then output goes high, and then it's strobed before data pins are >>> ready? Or does CS signal when the operation is complete after OE or >>> WE go high? >>> >>> Or are they something else entirely? :-) >> >> I would not be sure that applies to any application but is what the demo >> does, as they do not know what you will end up doing with the I/O pins. > > I think it's chip select. It looks like there are 17 address pins. 2^17 > yields 128 KB. The data reads/writes are 8-bits each, so I presume I will > be reading/writing 8 bits at that byte-address. 2^17 * 8 = 1 MBit. The > specs say it has 2 MBit of SRAM, so I assume CS means chip select, and > could be thought of essentially as the 18th address pin? > > I couldn't find the video with the lessons. Do you have a link, Cecil? > > Best regards, > Rick C. Hodgin >Sorry, I forgot to add the link, but mind you the lesson is not for the Lattice board, but it's in VHDL which can be used with any board. Lesson 2 has the implementation including debouncing of buttons, and a state machine. < https://www.youtube.com/watch?v=pDE2qenDXKQ > Lesson 1 Basics < https://www.youtube.com/watch?v=uhxTgUSZvYE > Lesson 2 Button Debouncer, State Machine < https://www.youtube.com/watch?v=yoytRxOjA-A > Lesson 3 Oscilloscope, VGA output -- Cecil - k5nwa
Reply by ●June 3, 20162016-06-03
On Friday, June 3, 2016 at 6:01:44 PM UTC-4, Cecil Bayona wrote:> On 6/3/2016 2:46 PM, Rick C. Hodgin wrote: > > On Friday, June 3, 2016 at 3:42:54 PM UTC-4, Cecil Bayona wrote: > >> On 6/3/2016 2:29 PM, Rick C. Hodgin wrote: > >>> Specs: > >>> > >>> http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/JL/LatticeXP2Brevia2DevelopmentKitUsersGuide.PDF?document_id=43735 > >>> > >>> In looking at the specs, it shows that all five momentary push buttons > >>> are already debounced, and 3 of the 4 DIP switches are (4 to 5 is not, > >>> pin 55). > >>> > >>> Awesome. Should make it easier. > >>> > >>> What are pins 142, 143, 144 (SRAM_CSb, SRAM_OEb, SRAM_WEb). I assume > >>> output enable and write enable? But what is CS? Some kind of strobe? > >>> Do the address and data pins go high, and write goes high, and then > >>> it's strobed before it actually writes? Or address pins go high, and > >>> then output goes high, and then it's strobed before data pins are > >>> ready? Or does CS signal when the operation is complete after OE or > >>> WE go high? > >>> > >>> Or are they something else entirely? :-) > >> > >> I would not be sure that applies to any application but is what the demo > >> does, as they do not know what you will end up doing with the I/O pins. > > > > I think it's chip select. It looks like there are 17 address pins. 2^17 > > yields 128 KB. The data reads/writes are 8-bits each, so I presume I will > > be reading/writing 8 bits at that byte-address. 2^17 * 8 = 1 MBit. The > > specs say it has 2 MBit of SRAM, so I assume CS means chip select, and > > could be thought of essentially as the 18th address pin? > > > > I couldn't find the video with the lessons. Do you have a link, Cecil? > > > > Best regards, > > Rick C. Hodgin > > > > Sorry, I forgot to add the link, but mind you the lesson is not for the > Lattice board, but it's in VHDL which can be used with any board. > > Lesson 2 has the implementation including debouncing of buttons, and a > state machine. > > < https://www.youtube.com/watch?v=pDE2qenDXKQ > Lesson 1 Basics > < https://www.youtube.com/watch?v=uhxTgUSZvYE > Lesson 2 Button > Debouncer, State Machine > < https://www.youtube.com/watch?v=yoytRxOjA-A > Lesson 3 Oscilloscope, > VGA outputI was able to go through this tonight. This type of design is very similar to what I plan for my Logician software: http://blog.bastelhalde.de/?p=678 I modified it so that the input buttons also map to additional LEDs, one each for the four inputs, to signal when they are pressed. But, I could not figure out how to do it without going through a dual inverter sequence. When I pulled the signal directly from the input pin, it would synthesize without error, but it would not illuminate the LED. I had to route it through the first inverter, then the second, and I'm sure about why that is. I'd like to begin working with timing and go through the stages to get a 640x480 VGA output working with an 8x6 font. Then, get a second Brevia2 to drive the VGA as a stand-alone hardware device communicating graphics updates over a simple protocol, allowing for dual-ported memory writes (one to SRAM, one to Video-RAM). Best regards, Rick C. Hodgin
Reply by ●June 4, 20162016-06-04
Rick C. Hodgin <rick.c.hodgin@gmail.com> wrote:> I think it's chip select. It looks like there are 17 address pins. 2^17 > yields 128 KB. The data reads/writes are 8-bits each, so I presume I will > be reading/writing 8 bits at that byte-address. 2^17 * 8 = 1 MBit. The > specs say it has 2 MBit of SRAM, so I assume CS means chip select, and > could be thought of essentially as the 18th address pin?CS is chip select. It's typically connected to the rest of your address decode logic: when you know you're talking to this chip and not something else, assert CS. However this is likely to be asynchronous SRAM, so the timing of CS and OE or WE set up the read or write cycle. I don't know the chip they use, but this is the datasheet for a traditional 'old fashioned' SRAM: http://6502.org/users/alexis/62256.pdf - see page 8. Since there isn't a clock going to the SRAM, you need to generate a cycle that meets the timing diagram from the chip you have. That means asserting signals in the right order and waiting the right length of time before you latch in any read data. Since the SRAM has no maximum time for an access cycle, you can just take it nice and slow by padding extra cycles in whatever clock you happen to use, and it should be fine, but you do still need to obey the right sequence. Theo
Reply by ●June 4, 20162016-06-04
Theo Markettos <theom+news@chiark.greenend.org.uk> wrote:> Rick C. Hodgin <rick.c.hodgin@gmail.com> wrote: >> I think it's chip select. It looks like there are 17 address pins. 2^17 >> yields 128 KB. The data reads/writes are 8-bits each, so I presume I will >> be reading/writing 8 bits at that byte-address. 2^17 * 8 = 1 MBit. The >> specs say it has 2 MBit of SRAM, so I assume CS means chip select, and >> could be thought of essentially as the 18th address pin? > > CS is chip select. It's typically connected to the rest of your address > decode logic: when you know you're talking to this chip and not something > else, assert CS. > > However this is likely to be asynchronous SRAM, so the timing of CS and OE or > WE set up the read or write cycle. I don't know the chip they use, but this > is the datasheet for a traditional 'old fashioned' SRAM: > http://6502.org/users/alexis/62256.pdf > - see page 8. > > Since there isn't a clock going to the SRAM, you need to generate a cycle > that meets the timing diagram from the chip you have. That means asserting > signals in the right order and waiting the right length of time before you > latch in any read data. Since the SRAM has no maximum time for an access > cycle, you can just take it nice and slow by padding extra cycles in > whatever clock you happen to use, and it should be fine, but you do still > need to obey the right sequence.I think the particular SRAM chip on the Lattice Brevia 2 board is of the true static kind. However, there are also certain pseudo-SRAM chips out there, i.e. DRAMs disguised behind an asynchronous, supposedly SRAM-compatible interface, which require CS to be deasserted every 15 us or so, in order to trigger DRAM's internal auto-refresh cycles. So don't take it for granted that CS is just an old-school chip select signal - it may be much more than that, and only digging into the datasheet of the particular chip can reveal its CS signal's true nature. Marko
Reply by ●June 4, 20162016-06-04
On 6/4/2016 8:17 AM, Marko Zec wrote:> Theo Markettos <theom+news@chiark.greenend.org.uk> wrote: >> Rick C. Hodgin <rick.c.hodgin@gmail.com> wrote: >>> I think it's chip select. It looks like there are 17 address pins. 2^17 >>> yields 128 KB. The data reads/writes are 8-bits each, so I presume I will >>> be reading/writing 8 bits at that byte-address. 2^17 * 8 = 1 MBit. The >>> specs say it has 2 MBit of SRAM, so I assume CS means chip select, and >>> could be thought of essentially as the 18th address pin? >> >> CS is chip select. It's typically connected to the rest of your address >> decode logic: when you know you're talking to this chip and not something >> else, assert CS. >> >> However this is likely to be asynchronous SRAM, so the timing of CS and OE or >> WE set up the read or write cycle. I don't know the chip they use, but this >> is the datasheet for a traditional 'old fashioned' SRAM: >> http://6502.org/users/alexis/62256.pdf >> - see page 8. >> >> Since there isn't a clock going to the SRAM, you need to generate a cycle >> that meets the timing diagram from the chip you have. That means asserting >> signals in the right order and waiting the right length of time before you >> latch in any read data. Since the SRAM has no maximum time for an access >> cycle, you can just take it nice and slow by padding extra cycles in >> whatever clock you happen to use, and it should be fine, but you do still >> need to obey the right sequence. > > I think the particular SRAM chip on the Lattice Brevia 2 board is of the > true static kind. However, there are also certain pseudo-SRAM chips > out there, i.e. DRAMs disguised behind an asynchronous, supposedly > SRAM-compatible interface, which require CS to be deasserted every > 15 us or so, in order to trigger DRAM's internal auto-refresh cycles. > So don't take it for granted that CS is just an old-school chip select > signal - it may be much more than that, and only digging into the > datasheet of the particular chip can reveal its CS signal's true nature. > > Marko >15 ns access time true static RAM chip. < http://www.idt.com/products/memory-logic/srams/asynchronous-srams/71v124-33v-128k-x-8-asynchronous-static-ram-center-power-ground-pinout > The board is not bad in terms of price ($43 at Mouser) for what you get, instant on, 128KB external RAM, 12 18x18 multipliers, 3 DSP Blocks, 400MHz FPGA core. Another slightly more expensive but with some extra features is the Papilio Duo for about $88 with Spartan 6 FPGA, 512 KB RAM (Optionally 2MB RAM), 8MB FLASH, that is bytes not bits, Arduino UNO with interface connectors, and a FPGA chip with 18 DSPslices. Too many toys, but not enough time. -- Cecil - k5nwa
Reply by ●June 4, 20162016-06-04
On Friday, June 3, 2016 at 10:27:07 PM UTC-4, Rick C. Hodgin wrote:> I was able to go through this tonight. This type of design is very > similar to what I plan for my Logician software: > > http://blog.bastelhalde.de/?p=678 > > I modified it so that the input buttons also map to additional LEDs, > one each for the four inputs, to signal when they are pressed. But, > I could not figure out how to do it without going through a dual > inverter sequence. When I pulled the signal directly from the input > pin, it would synthesize without error, but it would not illuminate > the LED. I had to route it through the first inverter, then the second, > and I'm sure about why that is. > > I'd like to begin working with timing and go through the stages to > get a 640x480 VGA output working with an 8x6 font. Then, get a second > Brevia2 to drive the VGA as a stand-alone hardware device communicating > graphics updates over a simple protocol, allowing for dual-ported memory > writes (one to SRAM, one to Video-RAM).I am presently hampered (to the point of significant failure) by knowing what I want to do, but not knowing the syntax to do it in Verilog (or VHDL). I'm tempted to begin working on my Logician tool so I can create its UI to operate the way I think. :-) Best regards, Rick C. Hodgin
