Custom timing on Altera Cyclone V GX dev board

On Friday, December 30, 2016 at 10:06:45 AM UTC-5, Rick C. Hodgin wrote:
> On Thursday, December 29, 2016 at 5:26:11 PM UTC-5, Theo Markettos wrote:
> > Rick C. Hodgin <rick.c.hodgin@gmail.com> wrote:
> > > I've been working on designing my L1 cache:
> > > 
> > >    https://github.com/RickCHodgin/libsf/tree/master/arxoda/core/cache_l1
> > >    https://github.com/RickCHodgin/libsf/blob/master/arxoda/core/cache_l1/cache1__4read_4write.png
> > > 
> > > And I'm about ready to program in a single 128-byte cache row and see
> > > if I can get it working.  I'm going to write it externally and produce
> > > Verilog code using gates and nets.
> > > 
> > > If I get it to a point where I think it's all there, but it's still
> > > not working, would you be willing to help me debug it?
> > 
> > I can't help you debug, since it's your design that only you know on
> > hardware only you have access to.  Debugging is a very personal penance.
> > 
> > However I suggest you have a look at ModelSim for simulation of your design
> > - Altera have a free version with some limitations.  For running on hardware
> > SignalTap gives you visibility of what's going on inside - with the
> > limitation that the number of signals and time are limited and it typically
> > involves frequent resynthesis cycles.  Hardware debugging can be slow and it
> > helps to think carefully about what you want to view before each synthesis
> > run - simulation has much better visibility shorter round-trip times, so it's
> > worth starting there unless you really need hardware.
> 
> I appreciate your input, Theo.  Thank you for your help.
> 
> I would prefer to do it in simulation.  I have plans to create a tool
> to do exactly that.  In fact, I've been building that cache design in
> both my mind and GIMP (graphics software).  With my simulation tool,
> called Logician, I would be able to create that basic image in a
> similar designer which is not just creating the image, but is connecting
> the wires together, having gate blocks which appear graphical as in my
> image, but contain underlying real logic.
> 
> I may go ahead and get that tool done so I can work on those things in
> simulation.  If I had that tool completed, I would actually like to
> complete my entire CPU and run it in simulation.

I want my Logician tool to function more or less like this logic sim
tool:

    https://www.kolls.net/gatesim/

    Screenshot:  https://www.kolls.net/gatesim/gatesim_ss.png

It has input, output, and an aggregation ability to create fundamental
circuits which can then be manipulated as larger constructs, as in the
image with the "half adder."

I want to provide noodle connections (as in that image), as well as
square/diagonal-routed lines.  I want to provide a "tactical" view
which shows things in block diagram concept, as well as a "details"
view which shows circuits, and to be able to enable those settings
on individual components within.  I want to be able to drill down
into an aggregation to see the fundamental circuits, and to be able
to leave those settings enabled in future views.

I also want to do it all in OpenGL because I eventually want to
create a process generation feature, which will physically generate
the circuits (in 3D) used for creating transistors on a substrate,
along with all wiring, placement, and routing.  I want it to give
users the ability to take concepts from idea, to design, to testing
and debugging, to physical layout and placement on a semiconductor
substrate.

My goals ultimately are to create a primitive fabrication facility
called Sand Castle Fabs, which uses antiquated process technologies
that are well mature and inexpensive to allow the creation of custom
ICs without the huge cost of modern fabs.  That's a goal I have for
the latter half of the 2020s. :-)

Best regards,
Rick C. Hodgin