Master Xilinx FPGA like Jtag bridge.

On Friday, March 24, 2017 at 10:08:43 PM UTC+6, Adam Górski wrote:
> >>>>>>> How to make master FPGA to connect to many FPGAs ?
> >>>>>>>
> >>>>>>> Two FPGAs connected by serial  TDI - TDO, and two fpgas  TMS TCK
> >>>>>>> TDO and TDI connect to master fpga, master fpga has TMS TDI TDO
> >>>>>>> TCK connected and working to pc normally, it need to make
> >>>>>>> connection JTAG of two fpgas to other 4 ports or somehow can
> >>>>>>> connect to master's jtag port ?
> >>>>>>
> >>>>>> |   |---------|-TMS----|------------|-TMS----
> >>>>>> |   | FPGA 0  |-TCK----|            |-TCK----
> >>>>>> |   |         |-TDO----|            |-TDO----
> >>>>>> |   |---------|        |            |-TDI----
> >>>>>> |       |              |            |
> >>>>>> |      TDI             |            |
> >>>>>> |       |              |            |
> >>>>>> |       |              | MASTER FPGA|
> >>>>>> |       |              |            |
> >>>>>> |      TDO             |            |
> >>>>>> |       |              |            |
> >>>>>> |   |---------|-TMS----|            |
> >>>>>> |   | FGPA 1  |-TCK----|            |
> >>>>>> |   |         |-TDI----|            |
> >>>>>> |   |---------|        |------------|
> >>>>>>
> >>>>>
> >>>>> Why do you want the master FPGA to control the others rather than
> >>>>> loading them all in one chain?  Connect all TMS and TCK lines in
> >>>>> parallel and connect all TDI and TDO in one big daisy chain.  If the
> >>>>> slave FPGAs are loaded by the master, where will the data come from?
> >>>> It is reverse engineering, someone did this but i just want reuse
> >>>> board only
> >>>
> >>> The JTAG signals to the master chip, do they connect to general I/Os as
> >>> well as to the FPGA JTAG signals?  Or just JTAG or just I/Os?
> >>>
> >>> You didn't say where you expect the data to come from to program the
> >>> chained slave FPGAs.  Is it supposed to come from the main JTAG port as
> >>> if it was talking to the slave chain?  Or will the master FPGA have a
> >>> separate interface from an MCU or a Flash chip?
> >>>
> >>> What is your overall plan?
> >> Slave FPGAs connects to USER I/O ports. for example:
> >> TMS of salve FPGA chip connects to user i/o pin  CC
> >> TDI of slave FPGA chip connects to user i/0 pin  VRP
> >> TCK of slave FPGA ship connects to user i/o pin  CC
> >
> > What do you connect the user I/O of the master to internally?  If you
> > try using the JTAG on the master it will control the master, no?
> >
> 
> Perhaps you are looking  for something similar like Altera JAM Player 
> for embedded.
> 
> Take a look here 
> https://www.altera.com/support/support-resources/support-centers/devices/programming-tools/jam-stapl/tls-jam-embedded.html
> 
> There is pice of C code able to send chip image from embedded system to 
> another fpga.
> 
> Unfortunatell I don't know X as good as I would like to.
> 
> BR
> 
> Adam

I dont know C