glitching AND gate

On Mon, 24 Apr 2017 16:36:15 -0700, Kevin Neilson wrote:

> Writing your own tools is probably quixotic.

No question that my own design tools (also a simulator) is quixotic.
Gotta dream big.

> The other way to provide timing is to have the logic signals themselves
> come with their own, inherent validity signal.  Delay insensitive (or
> quasi-delay insensitive) is the name for this idea and the dual-rail
> encoding that I referred to is one way to implement that.
> 
I don't know what you are trying to do but that description almost sounds like what Achronix was doing when they started out.  You'll observe, that despite their name, they eventually switched to synchronous logic.

On 4/26/2017 4:38 PM, Kevin Neilson wrote:
>> The other way to provide timing is to have the logic signals
>> themselves come with their own, inherent validity signal.  Delay
>> insensitive (or quasi-delay insensitive) is the name for this idea
>> and the dual-rail encoding that I referred to is one way to
>> implement that.
>>
> I don't know what you are trying to do but that description almost
> sounds like what Achronix was doing when they started out.  You'll
> observe, that despite their name, they eventually switched to
> synchronous logic.

When push came to shove the async logic aspect was not as important as 
it was to just make fast FPGAs which Achronix did by getting a leg up on 
the major FPGA players by using Intel's 22 nm FINFET technology.

The part I don't get is that Intel has bought Altera, so the fab service 
contract with Achronix is now competing with another Intel arm (pun 
intended).

-- 

Rick C

On Wed, 26 Apr 2017 13:38:11 -0700, Kevin Neilson wrote:

> I don't know what you are trying to do but that description almost
> sounds like what Achronix was doing when they started out.  You'll
> observe, that despite their name, they eventually switched to
> synchronous logic.

I'm not familiar with Achronix but I know of one other asynchronous FPGA
project that ended up being flushed.  Certainly this line of argument is
similar to a friend's who keeps pointing out to me that, while async was
more common back in the day, the entire industry has gone synchronous
since sometime back in the 1960s and so there must be a reason.  Yep,
probably.

What I'm thinking of is more along the lines of the Balsa synthesis
system from University of Manchester.

http://apt.cs.manchester.ac.uk/ftp/pub/apt/papers/FDL00.pdf
http://apt.cs.manchester.ac.uk/ftp/pub/apt/balsa/

> more common back in the day, the entire industry has gone synchronous
> since sometime back in the 1960s and so there must be a reason.  Yep,
> probably.
> 
> What I'm thinking of is more along the lines of the Balsa synthesis
> system from University of Manchester.

OK, as long as you know what you're getting into.  If you want to publish papers, that's great, but if you have something to deliver on a deadline, I'd avoid this whole line of thought...

Hi,

Am Sonntag, 23. April 2017 15:37:50 UTC+2 schrieb David Bridgham:
> And there's my question.  Will the AND gate implementation in an FPGA do
> that?  Or are LUTs odd enough that I can't depend on it?  If the answer
> is FPGA specific, I'm using an Artix 7 FPGA.

About the LUT itself a lot told you in this thread. 
But be aware that your verilog code will be optimized by synthesis tool. Usually synthesis tools don't care about glitch free result, so you need to ensure your final result is glitch free. 

regards Thomas