How To Provide External Input & Output To Startix 1S40..?

Hi,

I am trying to enable commmunication between two FPGAs, both being the
Stratix 1S40 on the Nios Stratix Boards. One chip implements a
controller while the other implements a datapath. I am trying to
provide control signals to the datapath-chip from the controller-chip
and retrieve back the output from the datapath-chip back to the
controller-chip. For this, I have assigned the outputs and inputs to
the pins of the Proto connnectors on the board and used the LVTTL IO
standard. For some reason, the communication doesn't seem to take
place. Subsequently, the connection between the FPGAs is then done
through IDE cables connected to the 40 pin Proto FDCs. Any settings
that I should be aware of when attempting to enable communication
through Proto connector pins..?

Thanks.

The main thing is to make sure setup and hold times are kept in check.
It will also work faster if all the signals are generated from the same chip
or you use bidirectional handshaking.
If your trying bi-directional coms... an LVDS seralizer would probably be
better... differential and fewer signals.


"Avin" <avin11@hotmail.com> wrote in message
news:30b48c91.0410192023.42dd4d5@posting.google.com...
> Hi,
>
> I am trying to enable commmunication between two FPGAs, both being the
> Stratix 1S40 on the Nios Stratix Boards. One chip implements a
> controller while the other implements a datapath. I am trying to
> provide control signals to the datapath-chip from the controller-chip
> and retrieve back the output from the datapath-chip back to the
> controller-chip. For this, I have assigned the outputs and inputs to
> the pins of the Proto connnectors on the board and used the LVTTL IO
> standard. For some reason, the communication doesn't seem to take
> place. Subsequently, the connection between the FPGAs is then done
> through IDE cables connected to the 40 pin Proto FDCs. Any settings
> that I should be aware of when attempting to enable communication
> through Proto connector pins..?
>
> Thanks.

"Avin" <avin11@hotmail.com> wrote in message 
news:30b48c91.0410192023.42dd4d5@posting.google.com...
> Hi,
>
> I am trying to enable commmunication between two FPGAs, both being the
> Stratix 1S40 on the Nios Stratix Boards. One chip implements a
> controller while the other implements a datapath. I am trying to
> provide control signals to the datapath-chip from the controller-chip
> and retrieve back the output from the datapath-chip back to the
> controller-chip. For this, I have assigned the outputs and inputs to
> the pins of the Proto connnectors on the board and used the LVTTL IO
> standard. For some reason, the communication doesn't seem to take
> place. Subsequently, the connection between the FPGAs is then done
> through IDE cables connected to the 40 pin Proto FDCs. Any settings
> that I should be aware of when attempting to enable communication
> through Proto connector pins..?
>
> Thanks.

I'm not sure if this is the source of your problem or not (assuming you have 
already checked trivial things and have simulated your design before going 
to the boards) but did you check your IDE cable? First, try to use a high 
quality, 80 pin IDE cable (i.e. the type used for UDMA-5 and 6 with one 
ground wire between each two signal wires). Also a long, parallel cable is 
not really the best way to make communication between two highspeed chips 
(it does not matter how fast your clock is, only the rising/falling edge of 
the signals that is controlled by the technology of the device is 
important). You'd better try a differntial, serial communication to have 
much better immunity against noise. 

I don't fully understand your requirements, but can you just join the
two boards together using an Ethernet switch? That would probably work
the best.
There are usually 3 issues joining two boards together as you've
suggested...

1) Power problems - make sure you have a good solid ground connection
between the boards - you can measure ground bounce between the boards
by grounding a scope probe on board A and measuring the ground on board
B.

2) Signal Integrity - make sure your signals are terminated correctly,
in particular the clock or latch signals. If you have reflections on a
clock or latch, the thing won't work no matter how slow it runs. You
can also mess with the slew rate and drive strength settings in
Quartus.

3) Timing problems - I'm assuming you're using a synchronous interface
(clock and data). On the transmitter, two techniques help here... a)
Use of I/O flip-flops and b) treating the output clock as an additional
data pin. If both clock and data are generated by the I/O flops, they
will all effectively have equal skew. On the receive side, you should
consider sampling the data on the opposite edge of the transmit clock
ie sample the data in the middle not at the transitions. You should
also look at the DQ/DQS structures on Stratix. They provide a dedicated
structure for clocking/latching external signals, but you might not
have access to them on the Stratix Board.

High speed serial is not a good choice unless you have a proper
connecter and routing scheme. If the 1S40 board is similar to my 1S10
board, this is not the case.

Good luck,
John

Avin wrote:

> Hi,
> 
> I am trying to enable commmunication between two FPGAs, both being the
> Stratix 1S40 on the Nios Stratix Boards. One chip implements a
> controller while the other implements a datapath. 
 >[snip]

To start with, you should attach a scope and look at some
signals. Do they leave the sender ?

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net