Spartan 2E and SDRAM

Hello,

I want to connect a SDRAM (single data rate) to a spartan 2e FPGA.
Are there some special recommendations about the attribution of the pins?

Thank you in advance

smu

smu wrote:
> Hello,
>
> I want to connect a SDRAM (single data rate) to a spartan 2e FPGA.
> Are there some special recommendations about the attribution of the
pins?
>
> Thank you in advance
>
> smu

I do this all the time in Spartan 2e with the lowest speed grade and
have no problem running 100 MHz with pinout selected before the code
was designed (i.e. the board was designed before the FPGA code).

Really you have to look at the speed you want to run and make sure
you can support the setup and hold requirements of the SDRAM parts
after the board is routed.  I usually pick the pinout to simplify
board routing, because in the end shorter traces lead to easier
timing constraints.

If you want to run the SDRAM at its rated frequency (usually at least
143 MHz) you need to be even more careful with layout.  Also my designs
were generally streaming video, so I didn't care about latency through
the memory, only throughput.  You will have trouble in any design that
doesn't use IOB flip-flops in both directions for data and output IOB
flip-flops on the control signals.

Remember to use fast slew on the outputs to reduce clock to out timing.
This also presents a challenge for quad flat packs which exhibit
significant ground bounce with multiple fast outputs switching.  I
would recommend BGA packaging, especially if you have a wide data bus.

If you need to use a PQ package for some reason, try to distribute the
data bus over multiple banks to reduce ground bounce.  This will
present
a routing challenge and may reduce the usable frequency of the final
design.