LVDS without termination

Symon wrote:
> Hi Gabor,
> I think the point is, that with tiny loads on the output, i.e. small
traces,
> the outputs swing very quickly to whatever voltage the current
sources can
> provide. This probably remains within the range of the FPGA's diff
inputs,
> they're very good and wide. I don't see how having 'guaranteed AC
content'
> makes any difference. Could you explain what you mean by that? Do you
mean
> enough edges, or no DC?
My point is that whether you model the lines as 50 ohm transmission
lines
with some finite delay, or as a lumped capacitive load, you will see
that
a current source switched into this net provides a slew-rate limited
output.  The slew rate should come directly from the current value and
the effective capacitance.
So if you had an ideal current source that never clipped, and didn't
have a DC balanced code, you would slowly integrate to one state or
another
and never return to the zero crossing.  In the case of a
voltage-limited
source, the issue is how much longer does it take to reach the
crossover
threshold if the outputs have a 2V differential (no load case having
been in one state long enough to clip the current source) than it would
to reach the crossover from a 0.35V differential (nominal LVDS into 100
ohms).
If the slew-rate limits you to a value that you can't accept at 480
Mbps you will need the resistors, not for termination but to limit the
output voltage swing.  For a true current source for example at 3.5mA
going into 10 pF, you would slew at most 0.35V per nanosecond.  From
the data sheet specs like ISOUT NP (outputs shorted together gives
12 mA max) I would guess these "current outputs" are not true current
sources, so the slew time may not be that bad.  However if the output
were really limited to 3.5 mA you could see that trying to slew 2V
would put you out of the realm of achieving 480 Mbps.
You may find that the drivers don't behave this way, but putting pads
for the 100 ohm terminators (even near the source) would give you a
way out if they do.
> As you say, I'd certainly have to try it first, the datasheet is not
clear
> on the output structure. See appnote HFAN-01.0 from Maxim for an
overview of
> their output structure. Dunno what the Texas one looks like.
> On the other hand, I'd be very nervous about doing this. Especially
with an
> enormous 80 pin PQFP package driving the outputs. Again, think of the
> hideous leadframe. Like you say, you'd have to prototype it first.
> Kolja,
> You do know that you can get 8x100 resistors in two packs sized
2x1mm? Rohm,
> AVX, Koa etc.. have gone to a lot of trouble to make these bits. Use
them!
> http://www.avx.com/docs/Catalogs/crb-crc.pdf
> And fix your PCB technology, your competitors will!
> Cheers, Syms.
>
> "Gabor" <gabor@alacron.com> wrote in message
> news:1107179024.417762.98680@f14g2000cwb.googlegroups.com...
> >
> > > at these very short signal lengths. What I am concerned about is
the
> > > current mode driver characteristic as described by Gabor.
> > What bothers me about leaving out terminators, especially in your
case
> > where you're not running 8b/10b or some other code with guaranteed
> > AC content, is what happens when the output has been in one state
long
> > enough to generate a wide voltage spread.

Kolja wrote:
>
> I am pretty sure that I can disregard transmission line effects
> at these very short signal lengths.
>
What's your planned routing scheme for the short differential nets?
( i.e.  track width/separation/height/etc per pair and between pairs,
# layer changes, # vias per net )

Also, if the A/D is only 4 mm distant from the FPGA, I'd start
worrying about power/gnd plane noise & bypass problems, and then
start considering moving it farther away :)

Or, are you splitting A/D and FPGA ground & power to provide
supply isolation, and then running coupled pairs across the
plane cuts to the FPGA?

>
> What I am concerned about is the  current mode driver
> characteristic as described by Gabor.
>
As for the unloaded behavior, I believe the driver output
impedance requirements (IIRC about 40-140 ohm single ended )
of the LVDS specs should bound the unloaded output swing.
( I'd add a third vote for the recommendation of verifying
that with your actual driver on an eval board )

I'd also vote for the suggestion of at least leaving room
for terminations where you can fit them near the driver; or,
if the pairs are crossing a plane cut, perhaps a fancier
differential/common mode attenuator scheme located right
at the plane cut would be in order.

If you have output driver strength control, you can tweak
that to reduce the output swing, whether unloaded or into
a higher-than-normal DCI termination value.

Brian

Kolja Sulimma wrote:
> Austin Lesea wrote at 2003-10-02 08:03:57 PST
> "Also look at what happens when you do not have a 100 ohm termination. 
> For some signals, and lengths of pcb, it may not be required." and
> "If I may suggest, use LVDCI_25_DCI only for clock inputs, or a few
> signals."
> 
> I need to get 16 LVDS pairs into one edge of a Spartan-3. This is really 
>  simple to layout without termination resistors and really complicated 
> (with our board technology) if I add termination resistors.
> 
> Without termination the maximum signal length is 4mm. The chip driving 
> the LVDS signals uses current mode output drivers.
> 
> My question now is what will happen if I try to use LVDS without 
> termination? Will the current mode drivers produce a very large output 
> signal swing? dangerous overshoot? (They are 3.3V powered)
> We want to run data at 480 Mbps over each pair so surely reflections 
> with less than 30ps roundtrip time are not that much of a problem?
> 
> If the current mode drivers require the 100R at their output, could I 
> add them at the source? To get many resistors much closer than 4mm on a 
> bga is difficult anyway.
> 
> Thank you in advance for your suggestions.

  On a short run, just where the termination is, is not as critical as 
having the temination itself.

  Fish-hooks in no termination at all, are likely to be :
a) Common mode range of the LVDS receivers - I do not believe this
is Rail-rail comparitor stuff - outside the common mode range two things 
might happen - slower recovery and/or logic inversion.
  Someone at xilinx should know ?

b) Simple dV/dT effects, will mean more intersymbol distortion effects
[assuming a) does not bite you first :) ]

you can get 4 resistors in a single package, and mount them 
routing-practical distances from the receiver ?

-jg

Hi Brian,
Comments below.

"Brian Davis" <brimdavis@aol.com> wrote in message
news:1107316023.395368.177070@c13g2000cwb.googlegroups.com...
> Kolja wrote:
>
> Also, if the A/D is only 4 mm distant from the FPGA, I'd start
> worrying about power/gnd plane noise & bypass problems, and then
> start considering moving it farther away :)
>
> Or, are you splitting A/D and FPGA ground & power to provide
> supply isolation, and then running coupled pairs across the
> plane cuts to the FPGA?
>
Ah well, here I go. This may generate some traffic.
Don't split the ground plane. Ever. It's your reference. I hear all this
stuff about currents flowing through the plane giving voltage noise. Doesn't
matter, with _proper_ bypassing, everything is coupled to the ground plane
so it all goes up and down locally with the plane anyway. Separate power is
of course a good idea, and in fact probably necessary. Each power area is
isolated from other power areas but tightly coupled to the ground plane
locally. As for your digital signals, keep them close to the ground plane
all the way to their destination.
Occasionally you'll see an app note from a ADC vendor saying you can use a
split plane, but all their sample/demo boards always have a single non-split
plane. I've come to think this is because they want to keep die-hard
plane-splitters using their parts. I guess these customers make a LOT of
prototypes!
Cheers, Syms.
p.s.
Hey Kolja, did you look at those resistor packs?

"Symon" <symon_brewer@hotmail.com> wrote in message
news:36cireF4vupthU1@individual.net...
> Ah well, here I go. This may generate some traffic.
> Don't split the ground plane. Ever. It's your reference.
Just to clarify, I'm not saying a split plane won't work. I'm saying that
with proper bypassing/decoupling it won't work any better than a single
plane.
Cheers, Syms.

Symon wrote:
>
> Just to clarify, I'm not saying a split plane won't work. I'm saying
> that with proper bypassing/decoupling it won't work any better than a
> single plane.
>
I didn't intend to wholeheartedly endorse splitting up the ground
plane, but only to question how Kolja was planning to lay out the
board, and suggest that appropriate care and attention be paid if
attempting such a crossing with the LVDS pairs in question.

Brian

Thanks to all of you for your replies. I am going to squeeze in the 
resistors somehow (the problem is to fit all the vias).

Kolja Sulimma

Jim Granville wrote
>  On a short run, just where the termination is, is not as critical as 
> having the temination itself.
[...]
> you can get 4 resistors in a single package, and mount them 
> routing-practical distances from the receiver ?
> 
> -jg
> 

Symon wrote:
> p.s.
> Hey Kolja, did you look at those resistor packs?
Yes I did. I used them in previous projects. The problem with this one 
are the vias.
I can run differential pairs nicely pitch matched from the 0.5mm pitch 
pqfp to the 1mm bga. Now 0.5mm single in line resistor packs would be 
graet (Pinout A1-A2-B1-B2-....). But dual in line resistor packs are 
rather useless unless I can route a signal between the pins.

I can't meet a 0.5mm via pitch, so the resistors can not sit at the back 
. And I can not have the vias on the inside of the PQFP (at least not 
all of them) because it is almost completely filled with a thermal pad.

But I am going to find a way to squeeze in the resistors....

Kolja

Kolja Sulimma wrote:
> Symon wrote:
> > p.s.
> > Hey Kolja, did you look at those resistor packs?
> Yes I did. I used them in previous projects. The problem with this
one
> are the vias.
> I can run differential pairs nicely pitch matched from the 0.5mm
pitch
> pqfp to the 1mm bga. Now 0.5mm single in line resistor packs would be

> graet (Pinout A1-A2-B1-B2-....). But dual in line resistor packs are
> rather useless unless I can route a signal between the pins.
>
> I can't meet a 0.5mm via pitch, so the resistors can not sit at the
back
> . And I can not have the vias on the inside of the PQFP (at least not

> all of them) because it is almost completely filled with a thermal
pad.
>
Check out Bourns CAT16-PT4F4 or CAT16-PT2F2.  These are 0.8mm, not 0.5
but they route through nicely on the surface (they're DIP but work like
a SIP because opposite pads connect together).

> But I am going to find a way to squeeze in the resistors....
> 
> Kolja

Gabor wrote:
> Kolja Sulimma wrote:
 >>Now 0.5mm single in line resistor packs would be
>>great (Pinout A1-A2-B1-B2-....). But dual in line resistor packs are
>>rather useless unless I can route a signal between the pins.
> 
> Check out Bourns CAT16-PT4F4 or CAT16-PT2F2.  These are 0.8mm, not 0.5
> but they route through nicely on the surface (they're DIP but work like
> a SIP because opposite pads connect together).

You are aware that I need to do parallel termination, not series 
termination? I use these resistor arrays a lot, but as you can not route 
  between the pins they are really inconvenient for LVDS parallel 
termination.

But we are really OT for this group now. Is there a sci.pcb.layout 
newgroup or something?
;-)

Kolja