some +. for Altera

"Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag
news:42495f4b$0$13468$91cee783@newsreader01.highway.telekom.at...
> >
> > Hi Thomas
> >
> > you have promised ERIC5 evaluation in MARCH 2005 there isnt much days
left
> > if you are about to keep that promise!
> >
> > Antti
> >
> >
>
> Hey, we are in FPGA business here, you should know marketing ;-) As you
say,
> there are still some days left...
>
> In fact I am just working on that eval-stuff. The first download will be
for
> the Nios-Cyclone-Kit, a second is planed for the Spartan-3-Starter-Kit.
The
> hardware will be fixed, but you will be able to write and download your
own
> software onto the board. There will be no eval-download for Actel, as the
> ProAsicPlus-Kit has no RS-232 (I do not think that people will start
> soldering a RS-232-adapter, just to test-drive ERIC5).
>
> Regards,
>
> Thomas
>
> www.entner-electronics.com
>
> P.S.: Of course, I'll try to keep my promise!

evaluation fixed to some specific kit are USELESS - really
I have 10+ evaluation boards but none of those you mentioned
so there will be no evaluation for me. And I am not going to
purchase an kit you support just to eval eric5, no way.

just my 2 cents. if you really are planning fixed to board-evals
you may as well not todo it at all

Antti

>
> evaluation fixed to some specific kit are USELESS - really
> I have 10+ evaluation boards but none of those you mentioned
> so there will be no evaluation for me. And I am not going to
> purchase an kit you support just to eval eric5, no way.
>
> just my 2 cents. if you really are planning fixed to board-evals
> you may as well not todo it at all
>
> Antti
>
>
Hmmm...

I hoped that I picked two boards that many people have (you really do not 
have the Digilent S3-board?)

I found no other useful solution that is both simple for the customer and 
protects our IP. Maybe you know one? (Please do not say: "Open Source", I 
had already this discussion ;-)

For Altera, there would be OpenCore plus, but you need to be an AMPP, and it 
is not easy to become that, so it does not help me.

Regards,

Thomas

www.entner-electronics.com

"Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag
news:42496f0b$0$25276$91cee783@newsreader02.highway.telekom.at...
> >
> > evaluation fixed to some specific kit are USELESS - really
> > I have 10+ evaluation boards but none of those you mentioned
> > so there will be no evaluation for me. And I am not going to
> > purchase an kit you support just to eval eric5, no way.
> >
> > just my 2 cents. if you really are planning fixed to board-evals
> > you may as well not todo it at all
> >
> > Antti
> >
> >
> Hmmm...
>
> I hoped that I picked two boards that many people have (you really do not
> have the Digilent S3-board?)
>
> I found no other useful solution that is both simple for the customer and
> protects our IP. Maybe you know one? (Please do not say: "Open Source", I
> had already this discussion ;-)
>
> For Altera, there would be OpenCore plus, but you need to be an AMPP, and
it
> is not easy to become that, so it does not help me.
>
> Regards,
>
> Thomas

Hi Thomas,

yes there is a way. In the matter of fact you could support Eric5 evaluation
an all
all any FPGA and board without knowing the board connections if you limit
the number Eric5 of ports being in used.

The solution is completly secure and doesnt require any 3rd party membership
programs or licensing. The question is if I tell you how to implement it and
even
provide some bare bones framework for it, what will there be for me?

Hm, once you asked the solution I have in mind thats quite nice solution,
well
I was thinking about the similar thing for another processor a few hours
ago -
that was for different purpose but the same approuch would be applicable for
Eric5 eval as well. Or in the matter of fact for eval of any softcore
processor :)

Antti
PS Thomas if interested, then we are off channel from now on this topic
use antti@truedream.org for direct email

Thomas Entner <aon.912710880@aon.at> wrote:
> >
> > evaluation fixed to some specific kit are USELESS - really
> > I have 10+ evaluation boards but none of those you mentioned
> > so there will be no evaluation for me. And I am not going to
> > purchase an kit you support just to eval eric5, no way.
> >
> > just my 2 cents. if you really are planning fixed to board-evals
> > you may as well not todo it at all
> >
> > Antti
> >
> >
> Hmmm...

> I hoped that I picked two boards that many people have (you really do not 
> have the Digilent S3-board?)

> I found no other useful solution that is both simple for the customer and 
> protects our IP. Maybe you know one? (Please do not say: "Open Source", I 
> had already this discussion ;-)

> For Altera, there would be OpenCore plus, but you need to be an AMPP, 
> and it is not easy to become that, so it does not help me.

What about distributing a core with some cycle counter that disables the
core after some cycles. I think there was a discussion about this "feature"
used by some vendor for distributing evaluation cores.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im
Newsbeitrag news:d2bso8$n9h$1@lnx107.hrz.tu-darmstadt.de...
> Thomas Entner <aon.912710880@aon.at> wrote:
> > >
> > > evaluation fixed to some specific kit are USELESS - really
> > > I have 10+ evaluation boards but none of those you mentioned
> > > so there will be no evaluation for me. And I am not going to
> > > purchase an kit you support just to eval eric5, no way.
> > >
> > > just my 2 cents. if you really are planning fixed to board-evals
> > > you may as well not todo it at all
> > >
> > > Antti
> > >
> > >
> > Hmmm...
>
> > I hoped that I picked two boards that many people have (you really do
not
> > have the Digilent S3-board?)
>
> > I found no other useful solution that is both simple for the customer
and
> > protects our IP. Maybe you know one? (Please do not say: "Open Source",
I
> > had already this discussion ;-)
>
> > For Altera, there would be OpenCore plus, but you need to be an AMPP,
> > and it is not easy to become that, so it does not help me.
>
> What about distributing a core with some cycle counter that disables the
> core after some cycles. I think there was a discussion about this
"feature"
> used by some vendor for distributing evaluation cores.
>
> Bye
> -- 
> Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

sure both Altera and Xilinx use evaluation timer method

the problem with Altera is that without being AMPP member its not possible
to distribute the core as encrypted version that is the core can only be
distributed
as either edif or flattened verilog/vhdl netlist, in bost cases disabling
the eval timer
would not be very problematic.

for Xilinx, well the eval timer of the EDK cores can be disabled very easily
:)
It's not a protection at all in the matter of fact. PLEASE dont ask me how.

Antti