Symon, I am suprised at you. Their white paper clearly shows the simualtion is done with the external termination, and not the internal one. Use the internal one, and the capacitance does not matter (do the sim yourself if you do not believe me). Of course, you really should use the LVDS where it is specified. If you want 1.3 Gbs, use our MGTs .... oh, I forgot, then do not have 2-GX parts .... The fact that their LVDS works up to 1.3 Gbs in simulation is nice, but can it be used in a real application on a real board? We have our ML450 Network Board for V4 to demonstrate 1 Gbs DDR interfaces, and it works just fine. Ask your FAE for a demo, or go online and buy the board. Austin Symon wrote:> "John_H" <johnhandwork@mail.com> wrote in message > news:OZbge.15$p%5.117@news-west.eli.net... > >>"Symon" <symon_brewer@hotmail.com> wrote in message >>news:42813fd3_2@x-privat.org... >> >><snip> >> >>>You might also like to look at this link. >>> >> > http://www.altera.com/products/devices/stratix2/utilities/st2-signal_integrity.html?f=tchio&k=g3 > >>>Altera claims their parts have a better LVDS 'eye' because they have >>>superior (i.e. less) pin capacitance. The capacitance gives a lot of > > ISI. > >><snip> >> >>But doesn't the Altera information use external LVDS terminations and >>monitor external to the part rather than internal terminations and the eye >>seen by the receiver? By looking outside the package that has an embedded >>differential termination, isn't the data skewed? >> >> > > I don't think so John. I think the whole white paper is based on a > simulation using the published Xilinx IBIS files. The terminations are > simulated as being on-chip. The Figure 1. in this document:- > http://www.altera.com/literature/wp/signal-integrity_s2-v4.pdf > is in the mind of an IBIS simulator, I guess. So, there are no physical > measurements. > Their data doesn't surprise me; 12.5pF of pin capacitance will really screw > with inter-symbol interference at Gbit rates. > Best, Syms. > >
Virtex4 running at 360Mhz DDR
Started by ●May 10, 2005
Reply by ●May 10, 20052005-05-10
Reply by ●May 11, 20052005-05-11
Austin,> > Use the internal one, and the capacitance does not matter > (do the sim yourself if you do not believe me). >Quoting Symon's last response [1] to such a misleading, incomplete, and inaccurate claim:>> >>Total bollocks >>And, just recently, some other Austin from Xilinx wrote [2]:>> >>Placing the cap at the receiver is really bad from a signal >>integrity standpoint: it makes for a huge reflection >>Exactly the point I was trying to make a couple years back, with which you disagreed so virulently. Rather than repeat my explanation of why high input C is bad, just re-read [3]. [ I agree that if the cap is right at the receiver in a point-point connection, all it will see is the filtered edge on the initial transition; but ignoring the aftereffects of that massive reflection is foolhardy. ]> > We have our ML450 Network Board for V4 to demonstrate 1 Gbs DDR > interfaces, and it works just fine. >The last time you said that, I asked [4]:>> Where in Xilinx's V4 documentation might one find these pictures >>and eye diagrams, including real world vs. simulated waveforms at >>the driver, receiver, and points in between ?Also from that thread, I suggested some other measurements to make on your "A vs. X" test platform:>> Since you have that spiffy board at hand, I'd love to see >> plots of the following: >> >> A) X vs. A ICCO for the "Hammer Test" at several toggle rates >> >> B1) X vs. A waveforms for a high speed single ended standard (xSTL)>> B2) X vs. A ICCO for a high speed single ended standard (xSTL) >> >> C1) X vs. A waveforms for 1 Gbps differential LVDS >> C2) X vs. A ICCO for 1 Gbps differential LVDS >> >> D) X vs. A differential TDR input waveforms into a DT termination >> at 100, 200, 500 ps input edge ratesWhen might we see some published data on those, particularly items C & D? Brian [1] http://groups-beta.google.com/group/comp.arch.fpga/msg/a6252d7a3566ea3f?hl=en [2] http://groups-beta.google.com/group/comp.arch.fpga/msg/7ef4d001e4d8ff65?hl=en [3] http://groups-beta.google.com/group/comp.arch.fpga/msg/a044806f313848e6?hl=en [4] http://groups-beta.google.com/group/comp.arch.fpga/msg/3619e923a589ef59?hl=en
Reply by ●May 11, 20052005-05-11
"austin" <austin@xilinx.com> wrote in message news:d5rp06$8034@cliff.xsj.xilinx.com...> Symon, > > I am suprised at you. Their white paper clearly shows the simualtion is > done with the external termination, and not the internal one. >Hmmm, so why do they say in Table 1. "Virtex-4 IBIS Models do Not Have Package Information"? How can they simulate the V4 package parasitics without this? Are you saying they're up to no good? It'd be interesting to see the Xilinx simulation from V4 LVDS output to V4 LVDS input.> > Use the internal one, and the capacitance does not matter (do the sim > yourself if you do not believe me). >I disagree. The Cpin of course limits the rise time at the pin. But also, and maybe worse, the capacitor at the input reflects a whole bunch of energy back down the T-line. The bigger the cap, the more energy is reflected. Some of this energy comes back again to the receiver after hitting the Cpin at the Tx end of the T-line. This causes inter-symbol interference. (Were you running your sim with a perfectly source terminated transmitter?)> > Of course, you really should use the LVDS where it is specified. If you > want 1.3 Gbs, use our MGTs .... oh, I forgot, then do not have 2-GX parts > .... >Stop changing the subject! You should be a politician! ;-) I did say your Rocket I/Os were a solution! And I bet they don't have 12.5pF of capacitance.> > The fact that their LVDS works up to 1.3 Gbs in simulation is nice, but > can it be used in a real application on a real board? >I'm pretty sure you're agreed IBIS simulations are a good idea. Works in simulation, should work in real life, right?> > We have our ML450 Network Board for V4 to demonstrate 1 Gbs DDR > interfaces, and it works just fine. Ask your FAE for a demo, or go online > and buy the board. > > Austin >Yep, Xilinx make great parts. They'd be even better with less Cpin though... Bloody customers want it all! ;-) Cheers, Syms.
Reply by ●May 11, 20052005-05-11
Brian, Get the ML450 board, or ask for the documentation. http://tinyurl.com/b2dmo Lots of scope shots are available (ask your FAE). or, http://www.xilinx.com/publications/prod_mktg/pn0010778.pdf (page 2) Or, go to one of our RocketLabs and measure it for yourself. As for the reflection, the LVDS transmitter is also a 100 ohm termination, so reflections are absorbed at the transmitter (when the LVDS is properly done and meets the specifications, which ours do). Anyone with an IBIS simulator can see all of the above happening, so I really don't want to take this any further - demanding to see scope shots of things is pretty pointless when the simulations are perfectly good (when they are done correctly). But, I am sure our Marketing Folks will be rolling our scope shots as part of pitch-packs, etc. for those who are unable or unwilling to do the SI engineering that their job requires of them. Austin
Reply by ●May 11, 20052005-05-11
Symon wrote:> "Symon" <symon_brewer@hotmail.com> wrote in message > news:4281198e$1_2@x-privat.org... > >>>- And how do you make the enable signal go on the global clock net? >>> >> >>You ask someone from Xilinx! I've not yet started my V4 design. I just >>remembered that from the marketing spiel we had. >>Cheers, Syms. >> > > Hmmm, I might have given you a bum steer there. I just looked at the FPGA > editor view of V4 and it seems there's NOT a path from the GBUFs to the CLB > CE. You can control a CE pin on the GBUF, but that's about as useful as a > chocolate teapot in this case. > Sorry about that, Syms.No you didn't bum steer... you were right initially. CE nets can be put onto a global clock network. Look at the CLB switch box in FPGA Editor again... each CE pin can be driven by a bounce pip (4 stubs in the middle right edge of the switch box), and these 4 bounces can all be driven by the GLK pips on the lower left edge of the switch box. There's your path. Cheers, Ajay Roopchansingh Xilinx Inc
Reply by ●May 11, 20052005-05-11
"Austin Lesea" <austin@xilinx.com> wrote in message news:d5t993$3041@cliff.xsj.xilinx.com...> > As for the reflection, the LVDS transmitter is also a 100 ohm > termination, so reflections are absorbed at the transmitter (when the > LVDS is properly done and meets the specifications, which ours do). >No. Not if this transmitter is a Xilinx FPGA with 12.5pF of parasitic capacitance. The high frequencies see a lower impedance, and so stuff relects back out of the transmitter, exactly the same as at the receiver. This is the point I'm trying to get you to understand. I tell you what, why don't you call that nice Dr. Howard Johnson and ask him? Here's a quote from National's LVDS manual. "In a good design the connector contributes 2 pF to 3 pF, the trace contributes 2 pF to 3 pF, and the device contributes 4 pF to 5 pF.The total load in such a design is around 10 pF. The flexibility of programmable devices comes at the cost of capacitance. National Bus LVDS products have an I/O capacitance of 5 pF. The I/O capacitance of a programmable device is approximately double or 10 pF. This increase in capacitance will lower the loaded bus impedance, thereby reducing the available noise margin and lowering the reliability of operation in the design." http://www.national.com/appinfo/lvds/files/ownersmanual.pdf> > Anyone with an IBIS simulator can see all of the above happening, so I > really don't want to take this any further - demanding to see scope > shots of things is pretty pointless when the simulations are perfectly > good (when they are done correctly). >I don't want to see scope shots, I agree I want to see a simulation 'done correctly'. I think I already have on Altera's website. Best regards, Syms.
Reply by ●May 11, 20052005-05-11
"Ajay Roopchansingh" <ajaytr@donotspam_xilinx.com> wrote in message news:d5t9ck$30d1@cliff.xsj.xilinx.com...> > No you didn't bum steer... you were right initially. CE nets can be put > onto a global clock network. Look at the CLB switch box in FPGA Editor > again... each CE pin can be driven by a bounce pip (4 stubs in the > middle right edge of the switch box), and these 4 bounces can all be > driven by the GLK pips on the lower left edge of the switch box. > There's your path. >Doh, Thanks Ajay. I see it now. Sneaky! Cheers, Syms.
Reply by ●May 11, 20052005-05-11
On Tue, 10 May 2005 19:02:19 -0700, austin <austin@xilinx.com> wrote:>The fact that their LVDS works up to 1.3 Gbs in simulation is nice, but >can it be used in a real application on a real board?Make up your mind Austin. On numerous occasions you have recommended that people run simulation of I/O systems to see what should happen, and you have recommened the IBIS models. To suggest that Altera does not know how to run simulations is insulting. Enough! Philip Freidin =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORG
Reply by ●May 11, 20052005-05-11
Symon, What is 12.5pF in series with 12.5pF? Yes, that is right, 6.25pF differential load, not 12.5pF. Falling for the A FUD is especially embarrassing when you just repeat things which are factually incorrect. All these things are taken into account from the simulation. Austin
Reply by ●May 11, 20052005-05-11
