Virtex4 running at 360Mhz DDR

Austin,

 Which of the following posts regarding Cin is more helpful
for both Xilinx and its' customers:

Austin [1]:
>
> Use the internal one, and the capacitance does not matter
> (do the sim yourself if you do not believe me).
>

Brian [2]:
>
>    At no point have I claimed that the V2 inputs are unusable,
>  but only that, in the presence of high speed drivers, extra
>  engineering effort needs to be expended to both understand the
>  impact of the V2 input capacitance on the interconnect, and
>  find a work-around that is appropriate for the design at hand.
>

Austin wrote:
>
>When folks wave their arms and state 12.5pF is the LVDS load,
>they are miss-stating it.
>
 The only I/O capacitance number published in your datasheet is a
single-ended parameter called Cin (or if you prefer, C_comp from
the IBIS files).

Quoting this published datasheet Cin value is perfectly valid,
and does not require "correction".

 Comparing that number against the single ended Cin's of other
devices, or against a single ended spec, is also perfectly valid.

 I have never said the differential load is 12.5 pf; it is clear
from my posts that I understand this, and also understand that
the assumption of Cdiff_effective = 1/2 Cin_single_ended applies
only for the differential components of the signals on the Tline.

 I find it rather inconsistent that in past discussions of
Xilinx's newly onerous SSO limits for the current mode output
drivers, you've been quite insistent that real world paths are
NOT perfectly balanced-

 Yet when discussing the effects of high Cin, you posit that
everything is perfectly balanced back to a perfect source
termination, so that a 50-60% voltage reflection off of your
input pins is never a problem.

 If only all FPGA input buffers could live happily ever after
there in Austin's world, where all connections are ideal
differential point-point links, all drivers have perfect back
terminations, and no probing or multidrops are ever allowed.

>
>In communications theory, excess bandwidth in the channel only adds
>to the error rate (due to noise).  Some band limiting is a good thing.
>
 And massive, coherent input reflections do not fit the AWGN
assumptions of most channel models, now do they?

Brian

p.s. As for your other post, I'll reply once I finish recovering
from a hard drive crash at home and can find my old files again.

[1]
http://groups-beta.google.com/group/comp.arch.fpga/msg/57bbb3ea78e194ed?hl=en
[2]
http://groups-beta.google.com/group/comp.arch.fpga/msg/a044806f313848e6?hl=en

Hi Austin,

Well, things are getting a little less busy with my day job, so I finally 
have time to start replying again... I figured I'd start with an easy one.

> The fact that their LVDS works up to 1.3 Gbs in simulation is nice, but 
> can it be used in a real application on a real board?

Yes.  Stratix II has LVDS running at 1.3 Gbps reliably across process, 
temperature, voltage.  Beautiful eye diagrams.  In simulation and on the 
board.  And as noted here 
(http://www.altera.com/products/devices/stratix2/features/performance/st2-perf_improvements.html), 
we will be increasing the spec to 1.25 Gbps in an upcoming version of 
Quartus II.

BTW, our simulations line up very will with board measurements.  We offer 
accurate IBIS models that we proudly stand behind.

Regards,

Paul Leventis
Altera Corp.

Austin:
> I am suprised at you.  Their white paper clearly shows the simualtion is 
> done with the external termination, and not the internal one.
> Use the internal one, and the capacitance does not matter (do the sim 
> yourself if you do not believe me).

According to our engineer who ran the sims, we did use on-chip termination 
for both V4 and Stratix II.  I read the whitepaper again 
(http://www.altera.com/literature/wp/signal-integrity_s2-v4.pdf) and I can't 
find anywhere where it says we didn't use on-chip termination.

> The fact that their LVDS works up to 1.3 Gbs in simulation is nice, but 
> can it be used in a real application on a real board?

Sorry to hammer on this again, but the above mentioned whitepaper does show 
some beautiful eye diagrams for SII and some ugly ones for V4.  It also 
shows how nicely our lab measurement (of 1.3 Gbps LVDS on Stratix II) 
compares to the IBIS simulation.

Regards,

Paul Leventis
Altera Corp.

Wait a minute - don't oversimply the original design critera - 720Mbps
DDR LVDS is only a part of my question.  The design also needs to run
the internals at 360Mhz, and that include portion of the fabric, not
just DSP48, etc.  Five years ago, I don't think so.  Maybe in the lab
somewhere, but not as an available product.

No problem.

That is what all of the wonderful features are for in V4 (SSIO, IODLY, 
DCM, etc.).  All of the above go a long way to support the fabric.  Even 
though the fabric will run at 500 MHz, it is far easier to mux it down 
to 200 MHz, or 100 MHz (using the built in SSIO features) which makes 
place and route easier, and also provides a lot of margin.

Just go buy the ML450 board (network interfaces), and you will get a 
fully working platform to test out all of your ~ 400 MHz up to 500 MHz 
DDR interfaces.

Austin

"Paul Leventis (at home)" <paulleventis-news@yahoo.ca> wrote in message
news:c9mdnXx_EujE9RTfRVn-2w@rogers.com...
>
> we will be increasing the spec to 1.25 Gbps in an upcoming version of
> Quartus II.
>
Paul,
Does that mean in Stratix II I could run an internal clock at 625MHz and use
the I/O DDR to move data out at 1.25Gbps?
Thanks, Syms.

Hi Symon,

There is a hard serializer/deserializer circuitry available for the
left and right LVDS I/O banks.  These SERDES blocks allow you to
deserialize/serialize by any factor between 4 and 10x.  For example,
you could bring in a 4x data bus running at 312.5 Mhz.  Or you can
bypass the SERDES block and use the DDR registers for a 2x SERDES.  Or
bypass completely for 1x... but not at 1.25 Gbps.  I don't know what
speed the SERDES/DDR I/O clock can run at or will run at when we update
this specification.  I'm sure it will be published at the time.

We also have dedicated Dynamic Phase Alignment (DPA) circuitry for
source-synchronous applications.  The DPA block enables you to
eliminate channel-to-channel and clock-to-channel skew.  It achieves
this by selecting the best clock phase to use for each I/O pair,
centering the sampling window in the eye.

Regards,

Paul Leventis
Altera Corp.

Symon,

According to the data sheet, you can run the LVDS I/O up to 500 MHz in
the fastest speed grade part.  That would get you 1 Gbps.  More likely,
you would use the SERDES.  For example, at 130 MHz and using x8
serialization, you get 1.04 Gbps per pair.  Here is a link to the DPA
datasheet:
http://www.altera.com/literature/hb/stx2/stx2_sii52005.pdf

John

Paul and John,
Thanks very much for your replies! So, for 1.25Gbps I'd need to use the
SERDES. I guess that means I have to use the PLL circuit to make the clock?
If I had more than 1 of these links, how easy is it to ensure that they're
all synchronised together. For example,
I want to send bits a_1, a_2, a_3, a_4 etc. on I/O LVDS_A
I want to send bits b_1, b_2, b_3, b_4 etc. on I/O LVDS_B
I use the serdes to do this. Can I ensure that a_n appears at (more or less)
the same time as b_n? I.e. that the shift registers in the two serdes are
aligned?
I know, I should read the bloody manual more carefully, but I couldn't find
this on a first pass.
Thanks, Syms.

"Paul Leventis" <paul.leventis@utoronto.ca> wrote in message
news:1116463566.371867.303600@g43g2000cwa.googlegroups.com...
> Hi Symon,
>
> There is a hard serializer/deserializer circuitry available for the
> left and right LVDS I/O banks.  These SERDES blocks allow you to
> deserialize/serialize by any factor between 4 and 10x.  For example,
> you could bring in a 4x data bus running at 312.5 Mhz.  Or you can
> bypass the SERDES block and use the DDR registers for a 2x SERDES.  Or
> bypass completely for 1x... but not at 1.25 Gbps.  I don't know what
> speed the SERDES/DDR I/O clock can run at or will run at when we update
> this specification.  I'm sure it will be published at the time.
>
> We also have dedicated Dynamic Phase Alignment (DPA) circuitry for
> source-synchronous applications.  The DPA block enables you to
> eliminate channel-to-channel and clock-to-channel skew.  It achieves
> this by selecting the best clock phase to use for each I/O pair,
> centering the sampling window in the eye.
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>

Hi Symon,

Sorry for taking so long to reply.

> I want to send bits a_1, a_2, a_3, a_4 etc. on I/O LVDS_A
> I want to send bits b_1, b_2, b_3, b_4 etc. on I/O LVDS_B
> I use the serdes to do this. Can I ensure that a_n appears at (more or 
> less)
> the same time as b_n? I.e. that the shift registers in the two serdes are
> aligned?

That's what the SERDES block is for.  You just need to instantiate a 
altlvds_rx (receiver) or altlvds_tx (transmitter) with the number of 
channels you want in the link.  Each of the channels will share a common 
PLL.  Therefore, they share a common clock, and the enable pulses derived 
from that clock.

And if you want to give the manual another stab ;-), I've been told that 
volume 2, chapter 5 of the Stratix II handbook, "High-Speed Differential I/O 
Interfaces with DPA in Stratix II Devices" 
http://www.altera.com/literature/hb/stx2/stx2_sii52005.pdf is helpful. 
Figures 5-2, 5-11 and 5-12 are most applicable in this case.

Regards,

Paul Leventis
Altera Corp.