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Altera why so QUIET !?

Started by Antti Lukats September 30, 2005
Hi

Altera used to make so much noise here, that I could not belive my eyes
seing Stratix-II GX devices at Altera website, and no posting about Altera
being the greatest at c.a.f. !!!

I guess the S2-GX actualy isnt available so its a wise decision to not yell
loud about it. I still wonder why the devices are listed on the web (without
datasheets!) at all at this time.

Sure its nice to see Altera claiming PCIe PIPE compliant serdes !

Antti


Hi Antti,

Glad to see you back!

> Altera used to make so much noise here, that I could not belive my eyes > seing Stratix-II GX devices at Altera website, and no posting about Altera > being the greatest at c.a.f. !!!
Personally, while not directly working for Altera, I'm pretty occupied with a six-week old son who unfortunately has inherited my aversion to sleep (instead of my wife's addiction to it) ;-) I guess Altera's a bit quiet because there's no huge news - the Virtex4 vs Stratix2 war is now fought in the field instead of the press, Quartus II version 5.1 isn't out yet (but soon, my friend, soon) and neither are Stratix2GX and Hardcopy2 (but which will give FaultyBits - er - EasyPath a run for its money very soon). Best regards, Ben
Ben,

Yes, it is nice to see Antti posting again.

By the way, if Altera doesn't use "faulty bits" why do you have:

1 	 6,759,871 		 Line segmentation in programmable logic devices having 
redundancy circuitry
2 	6,600,337 		Line segmentation in programmable logic devices having 
redundancy circuitry
3 	6,337,578 		Redundancy circuitry for programmable logic devices with 
interleaved input circuits
4 	6,222,382 		Redundancy circuitry for programmable logic devices with 
interleaved input circuits
5 	6,166,559 		Redundancy circuitry for logic circuits
6 	6,107,820 		Redundancy circuitry for programmable logic devices with 
interleaved input circuits
7 	6,091,258 		Redundancy circuitry for logic circuits
8 	6,034,536 		Redundancy circuitry for logic circuits
9 	5,498,975 		Implementation of redundancy on a programmable logic device

9 Patents (plus) for them?

Your use of laser frapped fuses to replace bad columns is identical to 
EasyPath (we just avoid the defects, the same as you).

'HardcopyTo' really does live up to its name:  not pin compatible, and a 
custom ASIC in every (bad) sense of the word.

Meanwhile, 'EasyPath' remains easy, and now includes the standard option 
of being able to change the logic (LUTs may be reprogrammed) or change 
the IO (strength).

Every try to ECO an ASIC?

With EasyPath, it is still just bits.

Austin
Hi Austin,

First of all, thanks for having been polite and courteous to everyone while
I was on paternity leave.

Second, to reiterate, I do _not_ work for Altera. I did, but I don't, and
haven't done so for several years. Thus, any reference to Altera with 'you'
when replying to my stuff is wrong.

> By the way, if Altera doesn't use "faulty bits" why do you have: > ... > 9 Patents (plus) for them?
Yep, and for you too. Not sure whether you actually had to use Altera's cross-licensed patents to make EasyPath see the light of day, but it surely must have saved on attorney fees, and $DEITY knows all of us should avoid feeding those critters.
> Your use of laser frapped fuses to replace bad columns is identical to > EasyPath (we just avoid the defects, the same as you).
Those patent cross-licensing deals are good, aren't they? To be honest, I always understood that EasyPath devices were carefully selected defective parts where the defect happened not to interfere with the specific user's design. Thanks for clarifying this. You just can't trust Marketing people these days.
> Meanwhile, 'EasyPath' remains easy, and now includes the standard option > of being able to change the logic (LUTs may be reprogrammed) or change > the IO (strength).
Just like with an FPGA... Ok, but now I'm thoroughly confused. Can you tell me, on a hardware level, what is the difference between your standard XC4Vxxx offering and its accompanying EasyPath device?
> Every try to ECO an ASIC?
Yep, and it's something best avoided. I FIBbed a few dies. Not fun, and I was a lucky bastard for getting two of the bloody things to work that way. Then it was bow-in-shame time for requesting a new mask from the boss... Best regards, Ben
Ben,

See below,

-snip-

> First of all, thanks for having been polite and courteous to everyone while > I was on paternity leave.
Congratulations.
> Second, to reiterate, I do _not_ work for Altera. I did, but I don't, and > haven't done so for several years. Thus, any reference to Altera with 'you' > when replying to my stuff is wrong.
I will remember that in future.
>>By the way, if Altera doesn't use "faulty bits" why do you have: >>... >>9 Patents (plus) for them? > > Yep, and for you too.
We do not use any laser, or other non-volatile methods to improve, or increase die yield (yet). Not sure whether you actually had to use Altera's
> cross-licensed patents to make EasyPath see the light of day,
Nope. but it surely
> must have saved on attorney fees, and $DEITY knows all of us should avoid > feeding those critters.
Altera's patent portfolio is quite respectable. So is ours. Due to the last legal settlement, I can not comment on any of it.
>>Your use of laser frapped fuses to replace bad columns is identical to >>EasyPath (we just avoid the defects, the same as you). > > Those patent cross-licensing deals are good, aren't they?
Again, no comment. I am all for avoiding those 'critters' as well...
> To be honest, I always understood that EasyPath devices were carefully > selected defective parts where the defect happened not to interfere with > the specific user's design. Thanks for clarifying this. You just can't > trust Marketing people these days.
Who at Xilinx every represented EasyPath as any other than what you described above? I understand Altera tells everyone EasyPath are "defective" parts. They also fail to mention that ALL of their parts use redundancy to repair defective portions of their FPGAs. At least our non-EasyPath FPGAs really have no defects whatsoever. EasyPath is tested to the customer's pattern, and represents an extremely high test coverage for their specific application. One advantage of EasyPath is that our method of testing provides a much higher quality part than ASIC testing is capable of.
>>Meanwhile, 'EasyPath' remains easy, and now includes the standard option >>of being able to change the logic (LUTs may be reprogrammed) or change >>the IO (strength). > > Just like with an FPGA... Ok, but now I'm thoroughly confused. Can you tell > me, on a hardware level, what is the difference between your standard > XC4Vxxx offering and its accompanying EasyPath device?
Absolutely nothing at all. No difference (in silicon). The EasyPath component is just tested (and marked) for a specific bitstream (or two). A customer can have a bistream for in-house manufacturing test, and another one for the application, or any two of their choice as an option. Try that with an ASIC sometimes!
>>Every try to ECO an ASIC? > > Yep, and it's something best avoided. I FIBbed a few dies. Not fun, and I > was a lucky bastard for getting two of the bloody things to work that way. > Then it was bow-in-shame time for requesting a new mask from the boss...
Then you can imagine what fun it is to do backside fib'ing of flip chip die. But, one advantage of "hardtocopy" is that Altera has to do the fib'ing when something doesn't work (not the customer). We just change bits and the customer keeps shipping, uninterrupted.
Austin Lesea <austin@xilinx.com> writes:
>> To be honest, I always understood that EasyPath devices were carefully >> selected defective parts where the defect happened not to interfere with >> the specific user's design.
This was my understanding as well. I think most people who take the time to read about it come to this conclusion.
> Who at Xilinx every represented EasyPath as any other than what you > described above?
Well, to be honest, going from the marketing materials alone, I wasn't quite sure if it was a new flavor of peanut butter or a boiled cabbage accelerator. But Xilinx's marketing department isn't really any worse than any other silicon valley company in that regard. ;)
> I understand Altera tells everyone EasyPath are "defective" parts. > They also fail to mention that ALL of their parts use redundancy to > repair defective portions of their FPGAs.
Interesting, I didn't know that.
> At least our non-EasyPath FPGAs really have no defects whatsoever.
Er, really? I thought you had to pay extra for the 100% tested ones. Does Xilinx really test every net on every chip for (say) stuck-at faults before shipping? - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380
Hi Austin,

> Who at Xilinx every represented EasyPath as any other than what you > described above?
I unfortunately don't get to talk to Xilinx people very often nowadays, which is a bit of a pity because I used to get along well with the whole Xilinx FAE team in Belgium - including Marc Defossez.
> I understand Altera tells everyone EasyPath are "defective" parts.
Well, they were presented to me as 'possibly partially defective parts, but happening to work OK with the specific customer design'.
> They also fail to mention that ALL of their parts > use redundancy to repair defective portions of their FPGAs.
Not quite true. When the EP20K1500E and its slightly less bulky brethren came out Altera quite proudly presented the redundancy as a yield improvement technique. The redundancy 'feature' was also present in Stratix customer presentations. I don't remember about Stratix II presentations though.
> At least our non-EasyPath FPGAs really have no defects whatsoever.
Oh, once Altera's repair department is done with a die, so does a Stratix (II), which is 100% tested as well.
> EasyPath is tested to the customer's pattern, and represents an > extremely high test coverage for their specific application.
So, can I then summarize that EasyPath is basically a standard Virtex II/4 but with less time on the testbed (only the cells and routing used by the customer are tested) in order to reduce cost? Best regards, Ben
Adam,

The "stuck at fault" testing is extremely high:  we carefully examine 
test patterns for their IC design shcematic coverage.

Even the generic FPGA flow test coverage is much better than an ASIC.

Austin


> Er, really? I thought you had to pay extra for the 100% tested ones. > Does Xilinx really test every net on every chip for (say) stuck-at > faults before shipping? > > - a >
Ben,

-snip-
> > > So, can I then summarize that EasyPath is basically a standard Virtex II/4 > but with less time on the testbed (only the cells and routing used by the > customer are tested) in order to reduce cost?
There is a basic 1's, 0's, shorts, leakage, etc test done to all parts, EasyPath or no. And then, for EasyPath, only those features used by the customer are tested (with the addition of any LUT pattern for the CLBs they use, and any IO strength for th IOB standard they use, which allows for the two most common ECO requests we got after we shipped). The difference in test time between as close as we can get to 100% testing for any possible use, and as close as we can get to 100% testing for one use is SIGNIFICANT. As well, the test yield to one test program is also SIGNIFICANTLY HIGHER than for many thousands of test programs (which is potentially what it takes to have an acceptable AQL). Better Yield + Shorter Time = Lower Cost to Xilinx, which means Lower Prices to customer. Austin
Ben -

Although I haven't used Xilinx' EasyPath product, it makes a fair
amount
of sense.  I've used V2Pro parts for a while, but I don't care about
or use the PowerPC processor I get in the the part.  EasyPath would
let me get cheaper parts in volume for 2 reasons -

a) Xilinx doesn't even have to test the PPC core in parts they would
ship
to me.  They save dollars because of chip test time saving.

b) Xilinx could send me parts with dead PPC cores since I don't use
that feature.  I assume the PPC core takes a reasonable amount of
silicon area, so it would have a reasonable chance of having a
defect.  Those 'dead' chips are currently lost revenue to Xilinx, the
incremental cost to sell them to me is fairly low.

I don't know how the EasyPath cost compares to the Altera HardCopy2,
but it sure makes sense that EasyPath could offer nice savings for
the volume user and additional profit for Xilinx.  A win-win situation.

John Providenza