DDR SDRAM Controller

Hi ada,

>This problem is caused due to Xilinx libraries. In the testbench, the DCM
>Reset is initially defined as "x",then it changes to "1". This initial
>transition is evaluated as a valid transition, and starts the DCM Reset
>lenght check from this transition, therefore causing the ERROR.

How do you generate the Reset,
do you you generate it in the testbench ?



Rgds
Andr=E9

>Any case I do not think I have to spend too much effort in order to bring
>the simulation to work because it's just a simulation. Nobody could
>guarantee that even if simulation works it would work with the real board.
>So I have to concentrate on a real board.

Yes, you are right.

But performing a timing simulation you can at least say that
your FPGA generates the timings correctly. For that
purpose I think it could be an advantage to use
a simple test case, for writing data to DDR memory and reading
it back (simplified data path)
Once proved you can concentrate on functional simulation
and static timing analysis.

Rgds
Andr=E9

Hello,

there is a problem with the reset signal in DCMs but it's nothing to do
with my design. I define rst signal for dcm in my ddr_sdr module (not in
my testbench) and initialize it with '0' but it's not the point. The point
is Xilinx libraries were buggy. Look here
http://www.xilinx-china.com/xlnx/xil_ans_printfriendly.jsp?getPagePath=18941
and here
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&getPagePath=19851&BV_SessionID=@@@@1915933191.1141761817@@@@&BV_EngineID=cccgaddhejdkhjgcefeceihdffhdfjf.0

Any case I ignored this error and also changed some libraries and DCM
locked. So now I could say that Post Synthesis looked ok. I have also just
done Post-Place & Route Simulation (with -sdfmax parameter) and I had lots
of warnings:

1) for all CKEs
Warning: CKE Setup time violation -- tIS
2) for all ddr_sdr_data_lo1_q (it's a low part of buffered data bus)
Warning: /X_FF SETUP   X  VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.182 ns; Observed := 0.129 ns; At : 207478.794 ns
3) for some ddr_sdr_data_hi_q (it's a high part of buffered data bus)
# ** Warning: /X_FF HOLD  Low VIOLATION ON CE WITH RESPECT TO CLK;
#   Expected := 0.028 ns; Observed := 0.016 ns; At : 207494.807 ns

I also saw lots of data glitches on data bus. But I have to look at the
simulation results more detailed and it's already too late. I think I
could tell more tomorrow.

Till tomorrow.

Hi all,

Post-Place & Route Simulation is ok now (I had some warnings due to data
glitches but I fixed it and everything works fine). Anyway there is no
progress with the board :( Do not know what I could possibly do. It seems
without an osci I am really lost. Or someone has an idea? I would be
really glad to hear any suggestions!

Best,
 Ada

Hi Ada,

ask Avnet if there is some DDR controller IP core evaluation bit stream
available for the board so that you can check whether DDR memory
accesses are possible and correct
at all. If they are correct then you know at least that you have to
analyze
your own controller.

Rgds
Andr=E9

Do you get DQS from the DDR memory if you send READ commands
to the memory ?

Rgds
Andr=E9

ALuPin@web.de schrieb:

> Do you get DQS from the DDR memory if you send READ commands
> to the memory ?
>=20
> Rgds
> Andr=E9

Ok, you already answered that question.

Avnet provides a test DDR SDRAM controller bit stream with their boards and
it works. That's why I'm sure it's my controller problem. But I how could I
find out it if even post-place&route simulation works fine? I'm out of
ideas.

>Could someone tell me about data IO's? I read that all data IO's must use
>both INFFs, OUTFFs and one of the Tristate-FFs (one could see it in mapper
>report). For me all data IO's use only OUTDDR...I am confused.

What are you doing with the data you read from the memory ?
Could it be that they are not used so that the synthesis tool
optimizes the complete read path away ?

Rgds
Andr=E9

>What are you doing with the data you read from the memory ?
>Could it be that they are not used so that the synthesis tool
>optimizes the complete read path away ?
>
>Rgds
>Andr=E9

Thanks that you're trying to help me. data is my 64-bit data bus. So as
you could see below I'm puting some data on the data bus during write op
using output buffer primitives and buffer the data bus using inpit buffers
for read op. 

GEN_D3: for n in 0 to DDR_DATA_WIDTH-1 generate

 DQ_OBUFT : OBUFT_SSTL2_II port map
 ( 
   I => d2sdr(n),
   T => tristate_q(n),
   O => data(n)
 );

 DQ_IBUF :  IBUF_SSTL2_II port map
 ( 
   I => data(n),
   O => read_data(n)
 );

end generate GEN_D3;

After I'm fetching low- and hi-words from the buffered data bus
(read_data) on rising and falling edges of the clock. So it does not seem
that the synthesis tool (XSE in my case) optimizes the complete read path
away.