DDR SDRAM Controller

Thanks to all guys!

For observing signals with an oscilloscope I really need a good one but I
found just an ordinary one. It does not seem to be very useful. I also
tried different DCM's PHASE_SHIFT values. I read a different data but no
correct one. So it was not the key. 

Could someone tell me about data IO's? I read that all data IO's must use
both INFFs, OUTFFs and one of the Tristate-FFs (one could see it in mapper
report). For me all data IO's use only OUTDDR...I am confused. 

ada schrieb:

> Thanks to all guys!
> 
> For observing signals with an oscilloscope I really need a good one but I
> found just an ordinary one. It does not seem to be very useful. I also

Those terms are not quite tecnically. An ordinary scope of today was a 
high end scope 5 years ago. What you need is some numbers. Last time I 
had a look at a DDR RAM interface I was using a 1.5 GHz scope form 
Agilent with 2.5 GHz active probes. Worked fine. Anyone had success 
using less firepower?

> tried different DCM's PHASE_SHIFT values. I read a different data but no
> correct one. So it was not the key. 
> 
> Could someone tell me about data IO's? I read that all data IO's must use
> both INFFs, OUTFFs and one of the Tristate-FFs (one could see it in mapper
> report). For me all data IO's use only OUTDDR...I am confused. 

This is just fine, OUTDDR are OUTFFs.

Regards
Falk

Hi Ada,

can you perform a timing simulation including timings and synthesis
results
of your FPGA ? You could at least see if timings of
DQS, DQ, RasN/CasN/WeN/CsN , ClkP, ClkN are correct when
coming out of the FPGA ...

Rgds
Andr=E9

>can you perform a timing simulation including timings and synthesis
>results
>of your FPGA ? You could at least see if timings of
>DQS, DQ, RasN/CasN/WeN/CsN , ClkP, ClkN are correct when
>coming out of the FPGA ...

I could perform only simulation using ModelSim. With ModelSim timings of
all signals which you mentioned are correct. With a real FPGA I could look
only at RasN/CasN/WeN/CsN signals when they come out of the FPGA. 

I think I did not mentioned my clocks. The board has 3 FPGA clocks -
40MHz, 66MHz and 125MHz. Currently I am using 125MHz FPGA clock
(input_clk). Then I have 2 DCMs from which I get clk, clk90 and clk270.
They both have fixed CLKOUT_PHASE_SHIFT, low DLL_FREQUENCY_MODE and sure
8.0 CLKIN_PERIOD. After using FDDRRSEs I generate ddr_clks from clk. I
tried to use different PHASE_SHIFT values but it did not really help.

Hi ada,

yes, Modelsim is the point. You can perform a timing simulation using
Modelsim that is you have to include the FPGA timing information file
(=2Esdf)
and the FPGA netlist (.vho) in your simulation. You have simulated
the VHDL description but not the synthesis result, am I right ?
Try to find out how to perform a timing simulation because that kind
of simulation shows real behavior of your FPGA.

Rgds
Andr=E9

> I could perform only simulation using ModelSim. With ModelSim timings of
> all signals which you mentioned are correct. With a real FPGA I could look
> only at RasN/CasN/WeN/CsN signals when they come out of the FPGA.
>
> I think I did not mentioned my clocks. The board has 3 FPGA clocks -
> 40MHz, 66MHz and 125MHz. Currently I am using 125MHz FPGA clock
> (input_clk). Then I have 2 DCMs from which I get clk, clk90 and clk270.
> They both have fixed CLKOUT_PHASE_SHIFT, low DLL_FREQUENCY_MODE and sure
> 8.0 CLKIN_PERIOD. After using FDDRRSEs I generate ddr_clks from clk. I
> tried to use different PHASE_SHIFT values but it did not really help.

ALuPin@web.de wrote:
> Hi ada,
>
> yes, Modelsim is the point. You can perform a timing simulation using
> Modelsim that is you have to include the FPGA timing information file
> (.sdf)
> and the FPGA netlist (.vho) in your simulation. You have simulated
> the VHDL description but not the synthesis result, am I right ?
> Try to find out how to perform a timing simulation because that kind
> of simulation shows real behavior of your FPGA.
>
> Rgds
> Andr=E9
>
> > I could perform only simulation using ModelSim. With ModelSim timings of
> > all signals which you mentioned are correct. With a real FPGA I could l=
ook
> > only at RasN/CasN/WeN/CsN signals when they come out of the FPGA.
> >
> > I think I did not mentioned my clocks. The board has 3 FPGA clocks -
> > 40MHz, 66MHz and 125MHz. Currently I am using 125MHz FPGA clock
> > (input_clk). Then I have 2 DCMs from which I get clk, clk90 and clk270.
> > They both have fixed CLKOUT_PHASE_SHIFT, low DLL_FREQUENCY_MODE and sure
> > 8.0 CLKIN_PERIOD. After using FDDRRSEs I generate ddr_clks from clk. I
> > tried to use different PHASE_SHIFT values but it did not really help.

While you are at it, get the simualation files from DDR vendors (here,
for example, is a typical page at Micron)
http://www.micron.com/products/dram/ddrsdram/part.aspx?part=3DMT46V128M4TG-=
5B

On the left, you'll see a range of available simulation models you can
integrate into your test bench.

Although this is not the same as a module, it's a lot closer than
nothing at all. A module will typically add some jitter and round trip
delay, but make sure your design works with a part used on the modules
first :)

Cheers

PeteS

 Thanks to all!

I simulated my design indeed using Micron memory models (I use
mt8vddt1664a memory model for simulation - it's not exactly my model but
seems to be closed enough for me) and as I wrote before it worked just
fine. But I did not use the FPGA netlist in my simulation. So as
ALuPin@web.de said I'd simulated the VHDL description but not the
synthesis result. I am going to simulate the synthesis results (I'll do it
tomorrow because first I have to find out how to do it. I've never done it
before). Does somebody have a good link about it? So I'm googling around.
I'll write about results tomorrow.

I am open to any other ideas.

Best,
 Ada

ada wrote:
> Thanks to all!
>
> I simulated my design indeed using Micron memory models (I use
> mt8vddt1664a memory model for simulation - it's not exactly my model but
> seems to be closed enough for me) and as I wrote before it worked just
> fine. But I did not use the FPGA netlist in my simulation. So as
> ALuPin@web.de said I'd simulated the VHDL description but not the
> synthesis result. I am going to simulate the synthesis results (I'll do it
> tomorrow because first I have to find out how to do it. I've never done it
> before). Does somebody have a good link about it? So I'm googling around.
> I'll write about results tomorrow.
>
> I am open to any other ideas.
>
> Best,
>  Ada

One thing I did not mention that *has* given me a great deal of grief
on DDR is Vref. DDR requires this to be V(mem) / 2 and the clock
crossings have to be within a tight range of this, to say nothing of
the other signals.

if Vref is produced by a resistive divider with a cap, you might have
an issue with just *some* memory sticks - they pull more from Vref than
the divider can stand (it's not stiff enough) and you'll get all sorts
of flaky (particularly read) behaviour. The standard behaviour of
devices is such that the current drawn from Vref is temperature
dependent, too, which you are seeing.

Stick a scope probe on Vref somewhere with a 'bad' stick and see if it
remains at the proper level (or if it even gets to the proper level).

Cheers

PeteS

PeteS wrote:
> One thing I did not mention that *has* given me a great deal of grief
> on DDR is Vref. DDR requires this to be V(mem) / 2 and the clock
> crossings have to be within a tight range of this, to say nothing of
> the other signals.
>
> if Vref is produced by a resistive divider with a cap, you might have
> an issue with just *some* memory sticks - they pull more from Vref than
> the divider can stand (it's not stiff enough) and you'll get all sorts
> of flaky (particularly read) behaviour. The standard behaviour of
> devices is such that the current drawn from Vref is temperature
> dependent, too, which you are seeing.
>
> Stick a scope probe on Vref somewhere with a 'bad' stick and see if it
> remains at the proper level (or if it even gets to the proper level).
>
> Cheers
>
> PeteS

Another point on using Virtex II and Vref.  The tools will
automatically
determine whether Vref is required for a particular bank based on the
inputs to that bank.  I have had a problem in the past where I did not
realize that my SSTL signals on one bank were all outputs (Address
and Control lines).  For this bank, I had the Vref pins tied to a
source
with a relatively high impedance.  The Vref pins were not required for
Vref on that bank and so the tools automatically defaulted them to
weak pullups.  The half dozen "weak" pullups were enough to bring the
Vref up to almost 2 volts.  This is worth checking if you are not using
all of the connections on the board, for example leaving out a feedback
input.  If you inadvertently free up the Vref pins on a bank they could
get you in trouble.  In my design I fixed the problem by setting the
BitGen defaults to "Float" for unused IOB pins.

Regards,
Gabor

Hi all,

sorry for keeping silence. I tried Post-Synthesis simulation with ModelSim
but I had an error:

# ** Error:  Timing Violation Error : RST on instance * must be asserted
for 3 CLKIN clock cycles. 
#    Time: 8100 ps  Iteration: 1  Process:
/tbx_top/i_top/i_ddr_sdr/dcm0/dcm_inst1/check_rst_width File:
C:/Programs/Xilinx/vhdl/src/unisims/unisim_VITAL.vhd

This problem is caused due to Xilinx libraries. In the testbench, the DCM
Reset is initially defined as "x",then it changes to "1". This initial
transition is evaluated as a valid transition, and starts the DCM Reset
lenght check from this transition, therefore causing the ERROR. 

So Xilinx proposes to update the software libraries. I did it but it did
not help. Does anyone have an idea how to fix it?
Any case I do not think I have to spend too much effort in order to bring
the simulation to work because it's just a simulation. Nobody could
guarantee that even if simulation works it would work with the real board.
So I have to concentrate on a real board. 

I asked AVNET about connecting an oscilloscope to the board but no answer
till now. And I have not found anything related to their boards and osci
connections in Internet.  

Does anyone have a working DDR SDRAM controller example? Or some other
ideas related to my problem? I would really appreciate it. 

And one more question. I am using 125MHz FPGA clock and I am giving clocks
with the same frequency (generated with DCM primitives ) to the DDR SDRAM.
I think it's ok but maybe I am mistaken. Does someone have other
suggestions?

Best,
 Ada