DDR SDRAM Controller

Hi all,
 could someone give me a tip about using DCMs?

I have seen many different memory interface clocking schemes but
unfortunately I did not find any explanation related to a general scheme
just different examples. Could someone explain it to me? I'd like to know
in which case which scheme I should use. 

I think I really have a clock synchronization problems but I can not check
it because I do not have an osci.  
I have 2 memory feedback clocks (feedback output and feedback input) -
clk_ddr_fb_out and clk_ddr_fb_in correspondingly. So clk_ddr_fb_out is
connected to ddr_clk and driven into the memory and clk_ddr_fb_in is
driven from the memory to my design. In my design two separate DCMs are
being used, one internal DCM for the memory controller design inside the
FPGA and the other external DCM to forward clocks to the external memory
device. Look at this picture. 
http://img115.imageshack.us/img115/6523/dcms1pv.jpg

But in this case DCM1 does not lock:( Am I doing something wrong? Any
ideas?