Xilinx ISE 6.3 confusion with CPLD logic results

My VHDL project has out grown a XC95108 CPLD, so I'll be using a
XC95144 instead.  After running the ISE synthesizer and fitter, all of
the XC95144's Function Block Inputs are used. Using exhaustive fit
mode, 92% of the function block inputs are used.  This still doesn't
leave much room for additional features.  I then told ISE to use a
XC95144XL, instead. Only 64% of the function block inputs are used, and

the other resources look good, too.  Even though the XL is a 3.3 volt
chip, it's 5 volt tolerant, so it should work.  The odd thing is that
the XL version uses _8 more_ flip flops than the standard version, and
the timing report shows that the XL is faster than the std part, even
though I selected 10 ns speed grade for both parts.  I haven't
simulated both chips yet.  There's lots of information in the Fitter
Report, but I don't know what I should be looking for.  I'm a bit
overwhelmed.  So far, the Xilinx docs haven't helped.
TIA,
-Dave Pollum

On Tue, 21 Feb 2006 14:37:43 -0800, Dave Pollum wrote:

> My VHDL project has out grown a XC95108 CPLD, so I'll be using a
> XC95144 instead.  After running the ISE synthesizer and fitter, all of
> the XC95144's Function Block Inputs are used. Using exhaustive fit
> mode, 92% of the function block inputs are used.  This still doesn't
> leave much room for additional features.  I then told ISE to use a
> XC95144XL, instead. Only 64% of the function block inputs are used, and
> the other resources look good, too. [...] The odd thing is that
> the XL version uses _8 more_ flip flops than the standard version, and
> the timing report shows that the XL is faster than the std part, even
> though I selected 10 ns speed grade for both parts.  I haven't
> simulated both chips yet.

The difference in flip-flop count could be due to the synthesiser using
another kind of implementation for some feature for your older CPLD. For
example, there are a couple of ways to encode a FSM, some being smaller and
others being a bit bigger but faster.

Secondly, the 10 ns speed grade only says something about the pad-to-pad
delay. If I recall correctly, this is the cumulative delay of a typical
signal path. Since the -XL is a whole different chip (3,3V instead of 5V
logic) the component delays making up the total delay are bound to
be different.

Hope that helps.

Wouter
-- 
Replace "spamtrap" with first name for email address.

Wouter Coene wrote:
> On Tue, 21 Feb 2006 14:37:43 -0800, Dave Pollum wrote:
>
> > My VHDL project has out grown a XC95108 CPLD, so I'll be using a
> > XC95144 instead.  After running the ISE synthesizer and fitter, all of
> > the XC95144's Function Block Inputs are used. Using exhaustive fit
> > mode, 92% of the function block inputs are used.  This still doesn't
> > leave much room for additional features.  I then told ISE to use a
> > XC95144XL, instead. Only 64% of the function block inputs are used, and
> > the other resources look good, too. [...] The odd thing is that
> > the XL version uses _8 more_ flip flops than the standard version, and
> > the timing report shows that the XL is faster than the std part, even
> > though I selected 10 ns speed grade for both parts.  I haven't
> > simulated both chips yet.
>
> The difference in flip-flop count could be due to the synthesiser using
> another kind of implementation for some feature for your older CPLD. For
> example, there are a couple of ways to encode a FSM, some being smaller and
> others being a bit bigger but faster.
>
> Secondly, the 10 ns speed grade only says something about the pad-to-pad
> delay. If I recall correctly, this is the cumulative delay of a typical
> signal path. Since the -XL is a whole different chip (3,3V instead of 5V
> logic) the component delays making up the total delay are bound to
> be different.
>
> Hope that helps.
>
> Wouter
> --
> Replace "spamtrap" with first name for email address.

Thanks!  Your comments do make me feel a bit better, but I'm still
curious about the different results.  I guess I'll re-read the XC9500
and XC9500XL docs.
-Dave Pollum